include/configs/ep8260.h

   1 /*
   2  * (C) Copyright 2002
   3  * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
   4  *
   5  * This file is based on similar values for other boards found in other
   6  * U-Boot config files, and some that I found in the EP8260 manual.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  *
  30  * "EP8260 H, V.1.1"
  31  *      - 64M 60x Bus SDRAM
  32  *      - 32M Local Bus SDRAM
  33  *      - 16M Flash (4 x AM29DL323DB90WDI)
  34  *      - 128k NVRAM with RTC
  35  *
  36  * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
  37  *      - 300MHz/133MHz/66MHz
  38  *      - 64M 60x Bus SDRAM
  39  *      - 32M Local Bus SDRAM
  40  *      - 32M Flash
  41  *      - 128k NVRAM with RTC
  42  */
  43
  44 #ifndef __CONFIG_H
  45 #define __CONFIG_H
  46
  47 /* Define this to enable support the EP8260 H2 version */
  48 #define CFG_EP8260_H2   1
  49 /* #undef CFG_EP8260_H2  */
  50
  51 #define CONFIG_CPM2             1       /* Has a CPM2 */
  52
  53 /* What is the oscillator's (UX2) frequency in Hz? */
  54 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  55
  56 /*-----------------------------------------------------------------------
  57  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  58  *-----------------------------------------------------------------------
  59  * What should MODCK_H be? It is dependent on the oscillator
  60  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  61  * Here are some example values (all frequencies are in MHz):
  62  *
  63  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  64  * -------   ----------  ---    ---    ----
  65  * 0x2       0x2         33     133    133
  66  * 0x2       0x3         33     133    166
  67  * 0x2       0x4         33     133    200
  68  * 0x2       0x5         33     133    233
  69  * 0x2       0x6         33     133    266
  70  *
  71  * 0x5       0x5         66     133    133
  72  * 0x5       0x6         66     133    166
  73  * 0x5       0x7         66     133    200 *
  74  * 0x6       0x0         66     133    233
  75  * 0x6       0x1         66     133    266
  76  * 0x6       0x2         66     133    300
  77  */
  78 #ifdef CFG_EP8260_H2
  79 #define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
  80 #else
  81 #define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
  82 #endif
  83
  84 /* Define this if you want to boot from 0x00000100. If you don't define
  85  * this, you will need to program the bootloader to 0xfff00000, and
  86  * get the hardware reset config words at 0xfe000000. The simplest
  87  * way to do that is to program the bootloader at both addresses.
  88  * It is suggested that you just let U-Boot live at 0x00000000.
  89  */
  90 /* #define CFG_SBC_BOOT_LOW 1 */        /* only for HRCW */
  91 /* #undef CFG_SBC_BOOT_LOW */
  92
  93 /* The reset command will not work as expected if the reset address does
  94  * not point to the correct address.
  95  */
  96
  97 #define CFG_RESET_ADDRESS       0xFFF00100
  98
  99 /* What should the base address of the main FLASH be and how big is
 100  * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
 101  * The main FLASH is whichever is connected to *CS0. U-Boot expects
 102  * this to be the SIMM.
 103  */
 104 #ifdef CFG_EP8260_H2
 105 #define CFG_FLASH0_BASE 0xFE000000
 106 #define CFG_FLASH0_SIZE 32
 107 #else
 108 #define CFG_FLASH0_BASE 0xFF000000
 109 #define CFG_FLASH0_SIZE 16
 110 #endif
 111
 112 /* What should the base address of the secondary FLASH be and how big
 113  * is it (in Mbytes)? The secondary FLASH is whichever is connected
 114  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
 115  * want it enabled, don't define these constants.
 116  */
 117 #define CFG_FLASH1_BASE 0
 118 #define CFG_FLASH1_SIZE 0
 119 #undef CFG_FLASH1_BASE
 120 #undef CFG_FLASH1_SIZE
 121
 122 /* What should be the base address of SDRAM DIMM (60x bus) and how big is
 123  * it (in Mbytes)?
 124 */
 125 #define CFG_SDRAM0_BASE 0x00000000
 126 #define CFG_SDRAM0_SIZE 64
 127
 128 /* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
 129  * local bus (8260 local bus is NOT cacheable!)
 130 */
 131 /* #define CFG_LSDRAM */
 132 #undef CFG_LSDRAM
 133
 134 #ifdef CFG_LSDRAM
 135 /* What should be the base address of SDRAM DIMM (local bus) and how big is
 136  * it (in Mbytes)?
 137 */
 138   #define CFG_SDRAM1_BASE 0x04000000
 139   #define CFG_SDRAM1_SIZE 32
 140 #else
 141   #define CFG_SDRAM1_BASE 0
 142   #define CFG_SDRAM1_SIZE 0
 143   #undef CFG_SDRAM1_BASE
 144   #undef CFG_SDRAM1_SIZE
 145 #endif /* CFG_LSDRAM */
 146
 147 /* What should be the base address of NVRAM and how big is
 148  * it (in Bytes)
 149  */
 150 #define CFG_NVRAM_BASE_ADDR  0xFA080000
 151 #define CFG_NVRAM_SIZE       (128*1024)-16
 152
 153 /* The RTC is a Dallas DS1556
 154  */
 155 #define CONFIG_RTC_DS1556
 156
 157 /* What should be the base address of the LEDs and switch S0?
 158  * If you don't want them enabled, don't define this.
 159  */
 160 #define CFG_LED_BASE 0x00000000
 161 #undef CFG_LED_BASE
 162
 163 /*
 164  * select serial console configuration
 165  *
 166  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 167  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 168  * for SCC).
 169  *
 170  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 171  * defined elsewhere.
 172  */
 173 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
 174 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
 175 #undef  CONFIG_CONS_NONE            /* define if console on neither */
 176 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
 177
 178 /*
 179  * select ethernet configuration
 180  *
 181  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 182  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 183  * for FCC)
 184  *
 185  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 186  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 187  * from CONFIG_COMMANDS to remove support for networking.
 188  */
 189 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
 190 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
 191 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 192 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 193
 194 #if ( CONFIG_ETHER_INDEX == 3 )
 195
 196 /*
 197  * - Rx-CLK is CLK15
 198  * - Tx-CLK is CLK16
 199  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 200  * - Enable Half Duplex in FSMR
 201  */
 202 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 203 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 204
 205 /*
 206  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 207  */
 208 #ifdef CFG_LSDRAM
 209   #define CFG_CPMFCR_RAMTYPE    3
 210 #else /* CFG_LSDRAM */
 211   #define CFG_CPMFCR_RAMTYPE    0
 212 #endif /* CFG_LSDRAM */
 213
 214 /* - Enable Half Duplex in FSMR */
 215 /* # define CFG_FCC_PSMR                (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 216 # define CFG_FCC_PSMR           0
 217
 218 #else /* CONFIG_ETHER_INDEX */
 219 # error "on EP8260 ethernet must be FCC3"
 220 #endif /* CONFIG_ETHER_INDEX */
 221
 222 /*
 223  * select i2c support configuration
 224  *
 225  * Supported configurations are {none, software, hardware} drivers.
 226  * If the software driver is chosen, there are some additional
 227  * configuration items that the driver uses to drive the port pins.
 228  */
 229 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 230 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 231 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 232 #define CFG_I2C_SLAVE           0x7F
 233
 234 /*
 235  * Software (bit-bang) I2C driver configuration
 236  */
 237 #ifdef CONFIG_SOFT_I2C
 238 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 239 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 240 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 241 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 242 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 243                         else    iop->pdat &= ~0x00010000
 244 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 245                         else    iop->pdat &= ~0x00020000
 246 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 247 #endif /* CONFIG_SOFT_I2C */
 248
 249 /* #define CONFIG_RTC_DS174x */
 250
 251 /* Define this to reserve an entire FLASH sector (256 KB) for
 252  * environment variables. Otherwise, the environment will be
 253  * put in the same sector as U-Boot, and changing variables
 254  * will erase U-Boot temporarily
 255  */
 256 #define CFG_ENV_IN_OWN_SECT
 257
 258 /* Define to allow the user to overwrite serial and ethaddr */
 259 #define CONFIG_ENV_OVERWRITE
 260
 261 /* What should the console's baud rate be? */
 262 #ifdef CFG_EP8260_H2
 263 #define CONFIG_BAUDRATE         9600
 264 #else
 265 #define CONFIG_BAUDRATE         115200
 266 #endif
 267
 268 /* Ethernet MAC address */
 269 #define CONFIG_ETHADDR          00:10:EC:00:30:8C
 270
 271 #define CONFIG_IPADDR           192.168.254.130
 272 #define CONFIG_SERVERIP         192.168.254.49
 273
 274 /* Set to a positive value to delay for running BOOTCOMMAND */
 275 #define CONFIG_BOOTDELAY        -1
 276
 277 /* undef this to save memory */
 278 #define CFG_LONGHELP
 279
 280 /* Monitor Command Prompt       */
 281 #define CFG_PROMPT              "=> "
 282
 283 /* Define this variable to enable the "hush" shell (from
 284    Busybox) as command line interpreter, thus enabling
 285    powerful command line syntax like
 286    if...then...else...fi conditionals or `&&' and '||'
 287    constructs ("shell scripts").
 288    If undefined, you get the old, much simpler behaviour
 289    with a somewhat smapper memory footprint.
 290 */
 291 #define CFG_HUSH_PARSER
 292 #define CFG_PROMPT_HUSH_PS2     "> "
 293
 294 /* What U-Boot subsytems do you want enabled? */
 295 /*
 296 */
 297 #define CONFIG_COMMANDS         ( CFG_CMD_ALL     & \
 298                                   ~(    CFG_CMD_BMP     | \
 299                                         CFG_CMD_BSP     | \
 300                                         CFG_CMD_DCR     | \
 301                                         CFG_CMD_DHCP    | \
 302                                         CFG_CMD_DISPLAY | \
 303                                         CFG_CMD_DOC     | \
 304                                         CFG_CMD_DTT     | \
 305                                         CFG_CMD_EEPROM  | \
 306                                         CFG_CMD_EXT2    | \
 307                                         CFG_CMD_FDC     | \
 308                                         CFG_CMD_FDOS    | \
 309                                         CFG_CMD_HWFLOW  | \
 310                                         CFG_CMD_IDE     | \
 311                                         CFG_CMD_JFFS2   | \
 312                                         CFG_CMD_KGDB    | \
 313                                         CFG_CMD_MII     | \
 314                                         CFG_CMD_MMC     | \
 315                                         CFG_CMD_NAND    | \
 316                                         CFG_CMD_PCI     | \
 317                                         CFG_CMD_PCMCIA  | \
 318                                         CFG_CMD_REISER  | \
 319                                         CFG_CMD_SCSI    | \
 320                                         CFG_CMD_SPI     | \
 321                                         CFG_CMD_UNIVERSE| \
 322                                         CFG_CMD_USB     | \
 323                                         CFG_CMD_VFD     | \
 324                                         CFG_CMD_XIMG    ) )
 325
 326
 327 /* Where do the internal registers live? */
 328 #define CFG_IMMR               0xF0000000
 329 #define CFG_DEFAULT_IMMR       0x00010000
 330
 331 /* Where do the on board registers (CS4) live? */
 332 #define CFG_REGS_BASE          0xFA000000
 333
 334 /*****************************************************************************
 335  *
 336  * You should not have to modify any of the following settings
 337  *
 338  *****************************************************************************/
 339
 340 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 341 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 342
 343 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
 344
 345 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 346 #include <cmd_confdefs.h>
 347
 348 /*
 349  * Miscellaneous configurable options
 350  */
 351 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 352 #  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
 353 #else
 354 #  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
 355 #endif
 356
 357 /* Print Buffer Size */
 358 #define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
 359
 360 #define CFG_MAXARGS       8            /* max number of command args   */
 361
 362 #define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
 363
 364 #ifdef CFG_LSDRAM
 365   #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
 366   #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 367 #else
 368   #define CFG_MEMTEST_START 0x00000000   /* memtest works on  */
 369   #define CFG_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
 370 #endif /* CFG_LSDRAM */
 371
 372 #define CONFIG_CLOCKS_IN_MHZ    1      /* clocks passsed to Linux in MHz */
 373
 374 #define CFG_LOAD_ADDR     0x00100000   /* default load address */
 375 #define CFG_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
 376
 377 #define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
 378
 379 /* valid baudrates */
 380 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 381
 382 /*
 383  * Low Level Configuration Settings
 384  * (address mappings, register initial values, etc.)
 385  * You should know what you are doing if you make changes here.
 386  */
 387
 388 #define CFG_FLASH_BASE    CFG_FLASH0_BASE
 389 #define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
 390
 391 /*-----------------------------------------------------------------------
 392  * Hard Reset Configuration Words
 393  */
 394
 395 #if defined(CFG_SBC_BOOT_LOW)
 396 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 397 #else
 398 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (0x00000000)
 399 #endif /* defined(CFG_SBC_BOOT_LOW) */
 400
 401 #ifdef CFG_EP8260_H2
 402 /* get the HRCW ISB field from CFG_DEFAULT_IMMR */
 403 #define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
 404                             ((CFG_DEFAULT_IMMR & 0x01000000) >> 7)  |\
 405                             ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
 406
 407 #define CFG_HRCW_MASTER (HRCW_EBM                |\
 408                          HRCW_L2CPC01            |\
 409                          CFG_SBC_HRCW_IMMR       |\
 410                          HRCW_APPC10             |\
 411                          HRCW_CS10PC01           |\
 412                          CFG_SBC_MODCK_H         |\
 413                          CFG_SBC_HRCW_BOOT_FLAGS)
 414 #else
 415 #define CFG_HRCW_MASTER 0x10400245
 416 #endif
 417
 418 /* no slaves */
 419 #define CFG_HRCW_SLAVE1 0
 420 #define CFG_HRCW_SLAVE2 0
 421 #define CFG_HRCW_SLAVE3 0
 422 #define CFG_HRCW_SLAVE4 0
 423 #define CFG_HRCW_SLAVE5 0
 424 #define CFG_HRCW_SLAVE6 0
 425 #define CFG_HRCW_SLAVE7 0
 426
 427 /*-----------------------------------------------------------------------
 428  * Definitions for initial stack pointer and data area (in DPRAM)
 429  */
 430 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 431 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 432 #define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
 433 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 434 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 435
 436 /*-----------------------------------------------------------------------
 437  * Start addresses for the final memory configuration
 438  * (Set up by the startup code)
 439  * Please note that CFG_SDRAM_BASE _must_ start at 0
 440  * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
 441  */
 442 #define CFG_MONITOR_BASE          TEXT_BASE
 443
 444
 445 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 446 #  define CFG_RAMBOOT
 447 #endif
 448
 449 #define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 450 #define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 451
 452 /*
 453  * For booting Linux, the board info and command line data
 454  * have to be in the first 8 MB of memory, since this is
 455  * the maximum mapped by the Linux kernel during initialization.
 456  */
 457 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 458
 459 /*-----------------------------------------------------------------------
 460  * FLASH and environment organization
 461  */
 462 #define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 463 #ifdef CFG_EP8260_H2
 464 #define CFG_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
 465 #else
 466 #define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 467 #endif
 468
 469 #ifdef CFG_EP8260_H2
 470 #define CFG_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
 471 #define CFG_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
 472 #else
 473 #define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 474 #define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 475 #endif
 476
 477 #ifndef CFG_RAMBOOT
 478 #  define CFG_ENV_IS_IN_FLASH  1
 479
 480 #  ifdef CFG_ENV_IN_OWN_SECT
 481 #    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
 482 #    define CFG_ENV_SECT_SIZE  0x40000
 483 #  else
 484 #    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
 485 #    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 486 #    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 487 #  endif /* CFG_ENV_IN_OWN_SECT */
 488 #else
 489 #  define CFG_ENV_IS_IN_NVRAM  1
 490 #  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 491 #  define CFG_ENV_SIZE         0x200
 492 #endif /* CFG_RAMBOOT */
 493
 494 /*-----------------------------------------------------------------------
 495  * Cache Configuration
 496  */
 497 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 498
 499 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 500 #  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 501 #endif
 502
 503 /*-----------------------------------------------------------------------
 504  * HIDx - Hardware Implementation-dependent Registers                    2-11
 505  *-----------------------------------------------------------------------
 506  * HID0 also contains cache control - initially enable both caches and
 507  * invalidate contents, then the final state leaves only the instruction
 508  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 509  * but Soft reset does not.
 510  *
 511  * HID1 has only read-only information - nothing to set.
 512  */
 513 #define CFG_HID0_INIT   (HID0_ICE  |\
 514                          HID0_DCE  |\
 515                          HID0_ICFI |\
 516                          HID0_DCI  |\
 517                          HID0_IFEM |\
 518                          HID0_ABE)
 519 #ifdef CFG_LSDRAM
 520 /* 8260 local bus is NOT cacheable */
 521 #define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
 522                          HID0_IFEM |\
 523                          HID0_ABE  |\
 524                          HID0_EMCP)
 525 #else /* !CFG_LSDRAM */
 526 #define CFG_HID0_FINAL  (HID0_ICE  |\
 527                          HID0_IFEM |\
 528                          HID0_ABE  |\
 529                          HID0_EMCP)
 530 #endif /* CFG_LSDRAM */
 531
 532 #define CFG_HID2        0
 533
 534 /*-----------------------------------------------------------------------
 535  * RMR - Reset Mode Register
 536  *-----------------------------------------------------------------------
 537  */
 538 #define CFG_RMR         0
 539
 540 /*-----------------------------------------------------------------------
 541  * BCR - Bus Configuration                                       4-25
 542  *-----------------------------------------------------------------------
 543  */
 544 #define CFG_BCR         (BCR_EBM   |\
 545                          BCR_PLDP  |\
 546                          BCR_EAV   |\
 547                          BCR_NPQM0)
 548
 549 /*-----------------------------------------------------------------------
 550  * SIUMCR - SIU Module Configuration                             4-31
 551  *-----------------------------------------------------------------------
 552  */
 553 #define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
 554                          SIUMCR_APPC10  |\
 555                          SIUMCR_CS10PC01)
 556
 557 /*-----------------------------------------------------------------------
 558  * SYPCR - System Protection Control                            11-9
 559  * SYPCR can only be written once after reset!
 560  *-----------------------------------------------------------------------
 561  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 562  */
 563 #ifdef CFG_EP8260_H2
 564 /* TBD: Find out why setting the BMT to 0xff causes the FCC to
 565  * generate TX buffer underrun errors for large packets under
 566  * Linux
 567  */
 568 #define CFG_SYPCR_BMT   0x00000600
 569 #else
 570 #define CFG_SYPCR_BMT   SYPCR_BMT
 571 #endif
 572
 573 #ifdef CFG_LSDRAM
 574 #define CFG_SYPCR       (SYPCR_SWTC |\
 575                          CFG_SYPCR_BMT  |\
 576                          SYPCR_PBME |\
 577                          SYPCR_LBME |\
 578                          SYPCR_SWP)
 579 #else
 580 #define CFG_SYPCR       (SYPCR_SWTC |\
 581                          CFG_SYPCR_BMT  |\
 582                          SYPCR_PBME |\
 583                          SYPCR_SWP)
 584 #endif
 585
 586 /*-----------------------------------------------------------------------
 587  * TMCNTSC - Time Counter Status and Control                     4-40
 588  *-----------------------------------------------------------------------
 589  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 590  * and enable Time Counter
 591  */
 592 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
 593                          TMCNTSC_ALR |\
 594                          TMCNTSC_TCF |\
 595                          TMCNTSC_TCE)
 596
 597 /*-----------------------------------------------------------------------
 598  * PISCR - Periodic Interrupt Status and Control                 4-42
 599  *-----------------------------------------------------------------------
 600  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 601  * Periodic timer
 602  */
 603 #ifdef CFG_EP8260_H2
 604 #define CFG_PISCR       (PISCR_PS  |\
 605                          PISCR_PTF |\
 606                          PISCR_PTE)
 607 #else
 608 #define CFG_PISCR       0
 609 #endif
 610
 611 /*-----------------------------------------------------------------------
 612  * SCCR - System Clock Control                                   9-8
 613  *-----------------------------------------------------------------------
 614  */
 615 #ifdef CFG_EP8260_H2
 616 #define CFG_SCCR        (SCCR_DFBRG00)
 617 #else
 618 #define CFG_SCCR        (SCCR_DFBRG01)
 619 #endif
 620
 621 /*-----------------------------------------------------------------------
 622  * RCCR - RISC Controller Configuration                         13-7
 623  *-----------------------------------------------------------------------
 624  */
 625 #define CFG_RCCR        0
 626
 627 /*-----------------------------------------------------------------------
 628  * MPTPR - Memory Refresh Timer Prescale Register               10-32
 629  *-----------------------------------------------------------------------
 630  */
 631 #define CFG_MPTPR       (0x0A00 & MPTPR_PTP_MSK)
 632
 633 /*
 634  * Init Memory Controller:
 635  *
 636  * Bank Bus     Machine PortSz  Device
 637  * ---- ---     ------- ------  ------
 638  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
 639  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
 640  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
 641  *  3   unused
 642  *  4   60x     GPCM     8 bit  Board Regs, NVRTC
 643  *  5   unused
 644  *  6   unused
 645  *  7   unused
 646  *  8   PCMCIA
 647  *  9   unused
 648  * 10   unused
 649  * 11   unused
 650 */
 651
 652 /*-----------------------------------------------------------------------
 653  * BRx - Base Register
 654  *     Ref: Section 10.3.1 on page 10-14
 655  * ORx - Option Register
 656  *     Ref: Section 10.3.2 on page 10-18
 657  *-----------------------------------------------------------------------
 658  */
 659
 660 /* Bank 0 - FLASH
 661  *
 662  */
 663 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
 664                          BRx_PS_64                      |\
 665                          BRx_DECC_NONE                  |\
 666                          BRx_MS_GPCM_P                  |\
 667                          BRx_V)
 668
 669 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
 670                          ORxG_CSNT                      |\
 671                          ORxG_ACS_DIV1                  |\
 672                          ORxG_SCY_8_CLK                 |\
 673                          ORxG_EHTR)
 674
 675 /* Bank 1 - SDRAM
 676  * PSDRAM
 677  */
 678 #define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 679                          BRx_PS_64                      |\
 680                          BRx_MS_SDRAM_P                 |\
 681                          BRx_V)
 682
 683 #define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
 684                          ORxS_BPD_4                     |\
 685                          ORxS_ROWST_PBI1_A6             |\
 686                          ORxS_NUMR_12)
 687
 688 #ifdef CFG_EP8260_H2
 689 #define CFG_PSDMR       0xC34E246E
 690 #else
 691 #define CFG_PSDMR       0xC34E2462
 692 #endif
 693
 694 #define CFG_PSRT        0x64
 695
 696 #ifdef CFG_LSDRAM
 697 /* Bank 2 - SDRAM
 698  * LSDRAM
 699  */
 700
 701   #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
 702                            BRx_PS_32                      |\
 703                            BRx_MS_SDRAM_L                 |\
 704                            BRx_V)
 705
 706   #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
 707                            ORxS_BPD_4                     |\
 708                            ORxS_ROWST_PBI0_A9             |\
 709                            ORxS_NUMR_12)
 710
 711   #define CFG_LSDMR      0x416A2562
 712   #define CFG_LSRT      0x64
 713 #else
 714   #define CFG_LSRT      0x0
 715 #endif /* CFG_LSDRAM */
 716
 717 /* Bank 4 - On board registers
 718  * NVRTC and BCSR
 719  */
 720 #define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 721                            BRx_PS_8                     |\
 722                            BRx_MS_GPCM_P                |\
 723                            BRx_V)
 724 /*
 725 #define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
 726                            ORxG_CSNT                   |\
 727                            ORxG_ACS_DIV1               |\
 728                            ORxG_SCY_10_CLK              |\
 729                            ORxG_TRLX)
 730 */
 731 #define CFG_OR4_PRELIM 0xfff00854
 732
 733 #ifdef _NOT_USED_SINCE_NOT_WORKING_
 734 /* Bank 8 - On board registers
 735  * PCMCIA (currently not working!)
 736  */
 737 #define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 738                            BRx_PS_16                     |\
 739                            BRx_MS_GPCM_P                |\
 740                            BRx_V)
 741
 742 #define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
 743                            ORxG_CSNT                   |\
 744                            ORxG_ACS_DIV1               |\
 745                            ORxG_SETA                   |\
 746                            ORxG_SCY_10_CLK)
 747 #endif
 748
 749 /*
 750  * Internal Definitions
 751  *
 752  * Boot Flags
 753  */
 754 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 755 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
 756
 757 /*
 758  * JFFS2 partitions
 759  *
 760  */
 761 /* No command line, one static partition, whole device */
 762 #undef CONFIG_JFFS2_CMDLINE
 763 #define CONFIG_JFFS2_DEV                "nor0"
 764 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 765 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 766
 767 /* mtdparts command line support */
 768 /* Note: fake mtd_id used, no linux mtd map file */
 769 /*
 770 #define CONFIG_JFFS2_CMDLINE
 771 #define MTDIDS_DEFAULT          ""
 772 #define MTDPARTS_DEFAULT        ""
 773 */
 774
 775 #endif  /* __CONFIG_H */