include/configs/ep82xxm.h

   1 /*
   2  * Copyright (C) 2006 Embedded Planet, LLC.
   3  *
   4  * U-Boot configuration for Embedded Planet EP82xxM boards.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 #define CONFIG_MPC8260
  29 #define CPU_ID_STR              "MPC8270"
  30
  31 #define CONFIG_EP82XXM  /* Embedded Planet EP82xxM H 1.0 board */
  32                         /* 256MB SDRAM / 64MB FLASH */
  33
  34 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f */
  35
  36 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  37 #define CONFIG_ENV_OVERWRITE
  38
  39 /*
  40  * Select serial console configuration
  41  *
  42  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  43  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  44  * for SCC).
  45  */
  46 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  47 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  48 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  49 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  50
  51 #define CFG_BCSR                0xFA000000
  52
  53 /*
  54  * Select ethernet configuration
  55  *
  56  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  57  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  58  * SCC, 1-3 for FCC)
  59  *
  60  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  61  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  62  * must be unset.
  63  */
  64 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  65 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  66 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  67
  68 #define CONFIG_NET_MULTI
  69
  70 #define CONFIG_ETHER_ON_FCC2
  71 #define CONFIG_ETHER_ON_FCC3
  72
  73 #define CFG_CMXFCR_MASK3        (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  74 #define CFG_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
  75 #define CFG_CMXFCR_MASK2        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  76 #define CFG_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  77
  78 #define CFG_CPMFCR_RAMTYPE      0
  79 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
  80
  81 #define CONFIG_MII                      /* MII PHY management        */
  82 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
  83
  84 /*
  85  * GPIO pins used for bit-banged MII communications
  86  */
  87 #define MDIO_PORT               0       /* Not used - implemented in BCSR */
  88 #define MDIO_ACTIVE             (*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
  89 #define MDIO_TRISTATE           (*(vu_char *)(CFG_BCSR + 8) |= 0x04)
  90 #define MDIO_READ               (*(vu_char *)(CFG_BCSR + 8) & 1)
  91
  92 #define MDIO(bit)               if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
  93                                 else    *(vu_char *)(CFG_BCSR + 8) &= 0xFE
  94
  95 #define MDC(bit)                if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
  96                                 else    *(vu_char *)(CFG_BCSR + 8) &= 0xFD
  97
  98 #define MIIDELAY                udelay(1)
  99
 100
 101 #ifndef CONFIG_8260_CLKIN
 102 #define CONFIG_8260_CLKIN       66000000 /* in Hz */
 103 #endif
 104
 105 #define CONFIG_BAUDRATE         115200
 106
 107 #define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
 108
 109
 110 /*
 111  * BOOTP options
 112  */
 113 #define CONFIG_BOOTP_BOOTFILESIZE
 114 #define CONFIG_BOOTP_BOOTPATH
 115 #define CONFIG_BOOTP_GATEWAY
 116 #define CONFIG_BOOTP_HOSTNAME
 117
 118
 119 /*
 120  * Command line configuration.
 121  */
 122 #include <config_cmd_default.h>
 123
 124
 125 #define CONFIG_CMD_DHCP
 126 #define CONFIG_CMD_ECHO
 127 #define CONFIG_CMD_I2C
 128 #define CONFIG_CMD_IMMAP
 129 #define CONFIG_CMD_MII
 130 #define CONFIG_CMD_PING
 131 #define CONFIG_CMD_DATE
 132 #define CONFIG_CMD_DTT
 133 #define CONFIG_CMD_EEPROM
 134 #define CONFIG_CMD_PCI
 135 #define CONFIG_CMD_DIAG
 136
 137
 138 #define CONFIG_ETHADDR          00:10:EC:00:88:65
 139 #define CONFIG_HAS_ETH1
 140 #define CONFIG_ETH1ADDR         00:10:EC:80:88:65
 141 #define CONFIG_IPADDR           10.0.0.245
 142 #define CONFIG_HOSTNAME         EP82xxM
 143 #define CONFIG_SERVERIP         10.0.0.26
 144 #define CONFIG_GATEWAYIP        10.0.0.1
 145 #define CONFIG_NETMASK          255.255.255.0
 146 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 147 #define CONFIG_ENV_IN_OWN_SECT  1
 148 #define CONFIG_AUTO_COMPLETE    1
 149 #define CONFIG_EXTRA_ENV_SETTINGS       "ethprime=FCC3 ETHERNET"
 150
 151 #if defined(CONFIG_CMD_KGDB)
 152 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 153 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 154 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 155 #define CONFIG_KGDB_INDEX       1       /* which serial channel for kgdb */
 156 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 157 #endif
 158
 159 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 160 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 161
 162 /*
 163  * Miscellaneous configurable options
 164  */
 165 #define CFG_HUSH_PARSER
 166 #define CFG_PROMPT_HUSH_PS2     "> "
 167 #define CFG_LONGHELP                    /* undef to save memory     */
 168 #define CFG_PROMPT              "ep82xxm=> "    /* Monitor Command Prompt   */
 169 #if defined(CONFIG_CMD_KGDB)
 170 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 171 #else
 172 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 173 #endif
 174 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size  */
 175 #define CFG_MAXARGS             16              /* max number of command args */
 176 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size  */
 177
 178 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 179 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 180
 181 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 182
 183 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 184
 185 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 186
 187 /*-----------------------------------------------------------------------
 188  * Environment
 189  *----------------------------------------------------------------------*/
 190 /*
 191  * Define here the location of the environment variables (FLASH or EEPROM).
 192  * Note: DENX encourages to use redundant environment in FLASH.
 193  */
 194 #if 1
 195 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 196 #else
 197 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars      */
 198 #endif
 199
 200 /*-----------------------------------------------------------------------
 201  * FLASH related
 202  *----------------------------------------------------------------------*/
 203 #define CFG_FLASH_BASE          0xFC000000
 204 #define CFG_FLASH_CFI
 205 #define CONFIG_FLASH_CFI_DRIVER
 206 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks       */
 207 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 208 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector in flinfo */
 209
 210 #ifdef CONFIG_ENV_IS_IN_FLASH
 211 #define CONFIG_ENV_SECT_SIZE    0x20000
 212 #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 213 #endif /* CONFIG_ENV_IS_IN_FLASH */
 214
 215 /*-----------------------------------------------------------------------
 216  * I2C
 217  *----------------------------------------------------------------------*/
 218 /* EEPROM Configuration */
 219 #define CFG_EEPROM_SIZE 0x1000
 220 #define CFG_I2C_EEPROM_ADDR     0x54
 221 #define CFG_I2C_EEPROM_ADDR_LEN 1
 222 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 223 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 224
 225 #ifdef CONFIG_ENV_IS_IN_EEPROM
 226 #define CONFIG_ENV_SIZE         0x200       /* Size of Environment vars */
 227 #define CONFIG_ENV_OFFSET               0x0
 228 #endif /* CONFIG_ENV_IS_IN_EEPROM */
 229
 230 /* RTC Configuration */
 231 #define CONFIG_RTC_M41T11       1       /* uses a M41T81 */
 232 #define CFG_I2C_RTC_ADDR        0x68
 233 #define CONFIG_M41T11_BASE_YEAR 1900
 234
 235 /* I2C SYSMON (LM75) */
 236 #define CONFIG_DTT_LM75         1
 237 #define CONFIG_DTT_SENSORS      {0}
 238 #define CFG_DTT_MAX_TEMP        70
 239 #define CFG_DTT_LOW_TEMP        -30
 240 #define CFG_DTT_HYSTERESIS      3
 241
 242 /*-----------------------------------------------------------------------
 243  * NVRAM Configuration
 244  *-----------------------------------------------------------------------
 245  */
 246 #define CFG_NVRAM_BASE_ADDR     0xFA080000
 247 #define CFG_NVRAM_SIZE          (128*1024)-16
 248
 249
 250 /*-----------------------------------------------------------------------
 251  * PCI stuff
 252  *-----------------------------------------------------------------------
 253  */
 254 /* General PCI */
 255 #define CONFIG_PCI                      /* include pci support          */
 256 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 257 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 258 #define CONFIG_PCI_BOOTDELAY    0
 259
 260 /* PCI Memory map (if different from default map */
 261 #define CFG_PCI_SLV_MEM_LOCAL   CFG_SDRAM_BASE          /* Local base */
 262 #define CFG_PCI_SLV_MEM_BUS             0x00000000      /* PCI base */
 263 #define CFG_PICMR0_MASK_ATTRIB  (PICMR_MASK_512MB | PICMR_ENABLE | \
 264                                  PICMR_PREFETCH_EN)
 265
 266 /*
 267  * These are the windows that allow the CPU to access PCI address space.
 268  * All three PCI master windows, which allow the CPU to access PCI
 269  * prefetch, non prefetch, and IO space (see below), must all fit within
 270  * these windows.
 271  */
 272
 273 /*
 274  * Master window that allows the CPU to access PCI Memory (prefetch).
 275  * This window will be setup with the second set of Outbound ATU registers
 276  * in the bridge.
 277  */
 278
 279 #define CFG_PCI_MSTR_MEM_LOCAL  0x80000000          /* Local base */
 280 #define CFG_PCI_MSTR_MEM_BUS    0x80000000          /* PCI base   */
 281 #define CFG_CPU_PCI_MEM_START   PCI_MSTR_MEM_LOCAL
 282 #define CFG_PCI_MSTR_MEM_SIZE   0x20000000          /* 512MB */
 283 #define CFG_POCMR0_MASK_ATTRIB  (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 284
 285 /*
 286  * Master window that allows the CPU to access PCI Memory (non-prefetch).
 287  * This window will be setup with the second set of Outbound ATU registers
 288  * in the bridge.
 289  */
 290
 291 #define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
 292 #define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
 293 #define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
 294 #define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 295 #define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 296
 297 /*
 298  * Master window that allows the CPU to access PCI IO space.
 299  * This window will be setup with the first set of Outbound ATU registers
 300  * in the bridge.
 301  */
 302
 303 #define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
 304 #define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
 305 #define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
 306 #define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
 307 #define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 308
 309
 310 /* PCIBR0 - for PCI IO*/
 311 #define CFG_PCI_MSTR0_LOCAL             CFG_PCI_MSTR_IO_LOCAL           /* Local base */
 312 #define CFG_PCIMSK0_MASK                ~(CFG_PCI_MSTR_IO_SIZE - 1U)    /* Size of window */
 313 /* PCIBR1 - prefetch and non-prefetch regions joined together */
 314 #define CFG_PCI_MSTR1_LOCAL             CFG_PCI_MSTR_MEM_LOCAL
 315 #define CFG_PCIMSK1_MASK                ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
 316
 317
 318 #define CFG_DIRECT_FLASH_TFTP
 319
 320 #if defined(CONFIG_CMD_JFFS2)
 321 #define CFG_JFFS2_FIRST_BANK    0
 322 #define CFG_JFFS2_NUM_BANKS     CFG_MAX_FLASH_BANKS
 323 #define CFG_JFFS2_FIRST_SECTOR  0
 324 #define CFG_JFFS2_LAST_SECTOR   62
 325 #define CFG_JFFS2_SORT_FRAGMENTS
 326 #define CFG_JFFS_CUSTOM_PART
 327 #endif
 328
 329 #if defined(CONFIG_CMD_I2C)
 330 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 331 #define CFG_I2C_SPEED           100000  /* I2C speed                    */
 332 #define CFG_I2C_SLAVE           0x7F    /* I2C slave address            */
 333 #endif
 334
 335 #define CFG_MONITOR_BASE        TEXT_BASE
 336 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 337 #define CFG_RAMBOOT
 338 #endif
 339
 340 #define CFG_MONITOR_LEN         (512 << 10)     /* Reserve 256KB for Monitor */
 341
 342 #define CFG_DEFAULT_IMMR        0x00010000
 343 #define CFG_IMMR                0xF0000000
 344
 345 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 346 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 347 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 348 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 349 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 350
 351
 352 /* Hard reset configuration word */
 353 #define CFG_HRCW_MASTER         0 /*0x1C800641*/  /* Not used - provided by CPLD */
 354 /* No slaves */
 355 #define CFG_HRCW_SLAVE1         0
 356 #define CFG_HRCW_SLAVE2         0
 357 #define CFG_HRCW_SLAVE3         0
 358 #define CFG_HRCW_SLAVE4         0
 359 #define CFG_HRCW_SLAVE5         0
 360 #define CFG_HRCW_SLAVE6         0
 361 #define CFG_HRCW_SLAVE7         0
 362
 363 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 364 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 365
 366 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 367 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 368
 369 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPUs */
 370 #if defined(CONFIG_CMD_KGDB)
 371 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 372 #endif
 373
 374 #define CFG_HID0_INIT           0
 375 #define CFG_HID0_FINAL          0
 376
 377 #define CFG_HID2                0
 378
 379 #define CFG_SIUMCR              0x02610000
 380 #define CFG_SYPCR               0xFFFF0689
 381 #define CFG_BCR                 0x8080E000
 382 #define CFG_SCCR                0x00000001
 383
 384 #define CFG_RMR                 0
 385 #define CFG_TMCNTSC             0x000000C3
 386 #define CFG_PISCR               0x00000083
 387 #define CFG_RCCR                0
 388
 389 #define CFG_MPTPR               0x0A00
 390 #define CFG_PSDMR               0xC432246E
 391 #define CFG_PSRT                0x32
 392
 393 #define CFG_SDRAM_BASE          0x00000000
 394 #define CFG_SDRAM_BR            (CFG_SDRAM_BASE | 0x00000041)
 395 #define CFG_SDRAM_OR            0xF0002900
 396
 397 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | 0x00001801)
 398 #define CFG_OR0_PRELIM          0xFC000882
 399 #define CFG_BR4_PRELIM          (CFG_BCSR | 0x00001001)
 400 #define CFG_OR4_PRELIM          0xFFF00050
 401
 402 #define CFG_RESET_ADDRESS       0xFFF00100
 403
 404 #endif /* __CONFIG_H */