include/configs/ethernut5.h

   1 /*
   2  * (C) Copyright 2011
   3  * egnite GmbH <info@egnite.de>
   4  *
   5  * Configuation settings for Ethernut 5 with AT91SAM9XE.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <asm/hardware.h>
  14
  15 /* The first stage boot loader expects u-boot running at this address. */
  16 #define CONFIG_SYS_TEXT_BASE    0x27000000      /* 16MB available */
  17
  18 /* The first stage boot loader takes care of low level initialization. */
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20
  21 /* Set our official architecture number. */
  22 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
  23
  24 /* CPU information */
  25 #define CONFIG_ARCH_CPU_INIT
  26
  27 /* ARM asynchronous clock */
  28 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768   /* slow clock xtal */
  29 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000 /* 18.432 MHz crystal */
  30
  31 /* 32kB internal SRAM */
  32 #define CONFIG_SRAM_BASE        0x00300000 /*AT91SAM9XE_SRAM_BASE */
  33 #define CONFIG_SRAM_SIZE        (32 << 10)
  34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
  35                                 GENERATED_GBL_DATA_SIZE)
  36
  37 /* 128MB SDRAM in 1 bank */
  38 #define CONFIG_NR_DRAM_BANKS            1
  39 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  40 #define CONFIG_SYS_SDRAM_SIZE           (128 << 20)
  41 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE
  42 #define CONFIG_LOADADDR                 CONFIG_SYS_LOAD_ADDR
  43 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (1 << 20))
  44 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  45 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE \
  46                                         - CONFIG_SYS_MALLOC_LEN)
  47
  48 /* 512kB on-chip NOR flash */
  49 # define CONFIG_SYS_MAX_FLASH_BANKS     1
  50 # define CONFIG_SYS_FLASH_BASE          0x00200000 /* AT91SAM9XE_FLASH_BASE */
  51 # define CONFIG_AT91_EFLASH
  52 # define CONFIG_SYS_MAX_FLASH_SECT      32
  53 # define CONFIG_SYS_FLASH_PROTECTION    /* First stage loader in sector 0 */
  54 # define CONFIG_EFLASH_PROTSECTORS      1
  55
  56 /* 512kB DataFlash at NPCS0 */
  57 #define CONFIG_SYS_MAX_DATAFLASH_BANKS  1
  58 #define CONFIG_HAS_DATAFLASH
  59 #define CONFIG_ATMEL_DATAFLASH_SPI
  60 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000
  61 #define DATAFLASH_TCSS                  (0x1a << 16)
  62 #define DATAFLASH_TCHS                  (0x1 << 24)
  63
  64 #define CONFIG_ENV_IS_IN_SPI_FLASH
  65 #define CONFIG_ENV_OFFSET               0x3DE000
  66 #define CONFIG_ENV_SECT_SIZE            (132 << 10)
  67 #define CONFIG_ENV_SIZE                 CONFIG_ENV_SECT_SIZE
  68 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
  69                                         + CONFIG_ENV_OFFSET)
  70 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
  71                                         + 0x042000)
  72
  73 /* SPI */
  74 #define CONFIG_ATMEL_SPI
  75 #define AT91_SPI_CLK                    15000000
  76
  77 /* Serial port */
  78 #define CONFIG_ATMEL_USART
  79 #define CONFIG_USART3                   /* USART 3 is DBGU */
  80 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  81 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  82
  83 /* Misc. hardware drivers */
  84 #define CONFIG_AT91_GPIO
  85
  86 /* Command line configuration */
  87 #define CONFIG_CMD_JFFS2
  88 #define CONFIG_CMD_MTDPARTS
  89 #define CONFIG_CMD_NAND
  90
  91 #ifndef MINIMAL_LOADER
  92 #define CONFIG_CMD_REISER
  93 #define CONFIG_CMD_SAVES
  94 #define CONFIG_CMD_UBIFS
  95 #endif
  96
  97 /* NAND flash */
  98 #ifdef CONFIG_CMD_NAND
  99 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 100 #define CONFIG_SYS_NAND_BASE            0x40000000
 101 #define CONFIG_SYS_NAND_DBW_8
 102 #define CONFIG_NAND_ATMEL
 103 /* our ALE is AD21 */
 104 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
 105 /* our CLE is AD22 */
 106 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
 107 #define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
 108 #endif
 109
 110 /* JFFS2 */
 111 #ifdef CONFIG_CMD_JFFS2
 112 #define CONFIG_JFFS2_CMDLINE
 113 #define CONFIG_JFFS2_NAND
 114 #endif
 115
 116 /* Ethernet */
 117 #define CONFIG_NET_RETRY_COUNT          20
 118 #define CONFIG_MACB
 119 #define CONFIG_RMII
 120 #define CONFIG_PHY_ID                   0
 121 #define CONFIG_MACB_SEARCH_PHY
 122
 123 /* MMC */
 124 #ifdef CONFIG_CMD_MMC
 125 #define CONFIG_GENERIC_ATMEL_MCI
 126 #define CONFIG_SYS_MMC_CD_PIN           AT91_PIO_PORTC, 8
 127 #endif
 128
 129 /* USB */
 130 #ifdef CONFIG_CMD_USB
 131 #define CONFIG_USB_ATMEL
 132 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 133 #define CONFIG_USB_OHCI_NEW
 134 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 135 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00500000
 136 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "host"
 137 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 138 #endif
 139
 140 /* RTC */
 141 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
 142 #define CONFIG_RTC_PCF8563
 143 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 144 #endif
 145
 146 /* I2C */
 147 #define CONFIG_SYS_MAX_I2C_BUS  1
 148
 149 #define CONFIG_SYS_I2C
 150 #define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 151 #define CONFIG_SYS_I2C_SOFT_SPEED       100000
 152 #define CONFIG_SYS_I2C_SOFT_SLAVE       0
 153
 154 #define I2C_SOFT_DECLARATIONS
 155
 156 #define GPIO_I2C_SCL            AT91_PIO_PORTA, 24
 157 #define GPIO_I2C_SDA            AT91_PIO_PORTA, 23
 158
 159 #define I2C_INIT { \
 160         at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
 161         at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
 162         at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
 163         at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
 164         at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
 165 }
 166
 167 #define I2C_ACTIVE      at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
 168 #define I2C_TRISTATE    at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
 169 #define I2C_SCL(bit)    at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
 170 #define I2C_SDA(bit)    at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
 171 #define I2C_DELAY       udelay(100)
 172 #define I2C_READ        at91_get_pio_value(AT91_PIO_PORTA, 23)
 173
 174 /* DHCP/BOOTP options */
 175 #ifdef CONFIG_CMD_DHCP
 176 #define CONFIG_BOOTP_BOOTFILESIZE
 177 #define CONFIG_BOOTP_BOOTPATH
 178 #define CONFIG_BOOTP_GATEWAY
 179 #define CONFIG_BOOTP_HOSTNAME
 180 #define CONFIG_SYS_AUTOLOAD     "n"
 181 #endif
 182
 183 /* File systems */
 184 #define CONFIG_MTD_DEVICE
 185 #define CONFIG_MTD_PARTITIONS
 186 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
 187 #define MTDIDS_DEFAULT          "nand0=atmel_nand"
 188 #define MTDPARTS_DEFAULT        "mtdparts=atmel_nand:-(root)"
 189 #endif
 190 #define CONFIG_LZO
 191 #define CONFIG_RBTREE
 192
 193 /* Boot command */
 194 #define CONFIG_CMDLINE_TAG
 195 #define CONFIG_SETUP_MEMORY_TAGS
 196 #define CONFIG_INITRD_TAG
 197 #define CONFIG_BOOTCOMMAND      "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
 198 #if defined(CONFIG_CMD_NAND)
 199 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 200                                 "root=/dev/mtdblock0 " \
 201                                 MTDPARTS_DEFAULT \
 202                                 " rw rootfstype=jffs2"
 203 #endif
 204
 205 /* Misc. u-boot settings */
 206 #define CONFIG_SYS_CBSIZE               256
 207 #define CONFIG_SYS_MAXARGS              16
 208 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + 16 \
 209                                         + sizeof(CONFIG_SYS_PROMPT))
 210 #define CONFIG_SYS_LONGHELP
 211 #define CONFIG_CMDLINE_EDITING
 212
 213 #endif