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1 /*
2 * (C) Copyright 2011
3 * egnite GmbH <info@egnite.de>
4 *
5 * Configuation settings for Ethernut 5 with AT91SAM9XE.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #include <asm/hardware.h>
14
15 /* The first stage boot loader expects u-boot running at this address. */
16 #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
17
18 /* The first stage boot loader takes care of low level initialization. */
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20
21 /* Set our official architecture number. */
22 #define MACH_TYPE_ETHERNUT5 1971
23 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
24
25 /* CPU information */
26 #define CONFIG_DISPLAY_CPUINFO /* Display at console. */
27 #define CONFIG_ARCH_CPU_INIT
28
29 /* ARM asynchronous clock */
30 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
31 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
32
33 /* 32kB internal SRAM */
34 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
35 #define CONFIG_SRAM_SIZE (32 << 10)
36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
37 GENERATED_GBL_DATA_SIZE)
38
39 /* 128MB SDRAM in 1 bank */
40 #define CONFIG_NR_DRAM_BANKS 1
41 #define CONFIG_SYS_SDRAM_BASE 0x20000000
42 #define CONFIG_SYS_SDRAM_SIZE (128 << 20)
43 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
44 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
45 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
46 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
47 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
48 - CONFIG_SYS_MALLOC_LEN)
49
50 /* 512kB on-chip NOR flash */
51 # define CONFIG_SYS_MAX_FLASH_BANKS 1
52 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
53 # define CONFIG_AT91_EFLASH
54 # define CONFIG_SYS_MAX_FLASH_SECT 32
55 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
56 # define CONFIG_EFLASH_PROTSECTORS 1
57
58 /* 512kB DataFlash at NPCS0 */
59 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
60 #define CONFIG_HAS_DATAFLASH
61 #define CONFIG_ATMEL_DATAFLASH_SPI
62 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
63 #define DATAFLASH_TCSS (0x1a << 16)
64 #define DATAFLASH_TCHS (0x1 << 24)
65
66 #define CONFIG_ENV_IS_IN_SPI_FLASH
67 #define CONFIG_ENV_OFFSET 0x3DE000
68 #define CONFIG_ENV_SECT_SIZE (132 << 10)
69 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
70 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
71 + CONFIG_ENV_OFFSET)
72 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
73 + 0x042000)
74
75 /* SPI */
76 #define CONFIG_ATMEL_SPI
77 #define AT91_SPI_CLK 15000000
78
79 /* Serial port */
80 #define CONFIG_ATMEL_USART
81 #define CONFIG_USART3 /* USART 3 is DBGU */
82 #define CONFIG_BAUDRATE 115200
83 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
84 #define CONFIG_USART_ID ATMEL_ID_SYS
85
86 /* Misc. hardware drivers */
87 #define CONFIG_AT91_GPIO
88
89 /* Command line configuration */
90 #define CONFIG_CMD_JFFS2
91 #define CONFIG_CMD_MII
92 #define CONFIG_CMD_MTDPARTS
93 #define CONFIG_CMD_NAND
94
95 #ifndef MINIMAL_LOADER
96 #define CONFIG_CMD_ASKENV
97 #define CONFIG_CMD_BSP
98 #define CONFIG_CMD_CACHE
99 #define CONFIG_CMD_DATE
100 #define CONFIG_CMD_EXT2
101 #define CONFIG_CMD_FAT
102 #define CONFIG_CMD_MMC
103 #define CONFIG_CMD_REISER
104 #define CONFIG_CMD_SAVES
105 #define CONFIG_CMD_UBI
106 #define CONFIG_CMD_UBIFS
107 #define CONFIG_CMD_UNZIP
108 #endif
109
110 /* NAND flash */
111 #ifdef CONFIG_CMD_NAND
112 #define CONFIG_SYS_MAX_NAND_DEVICE 1
113 #define CONFIG_SYS_NAND_BASE 0x40000000
114 #define CONFIG_SYS_NAND_DBW_8
115 #define CONFIG_NAND_ATMEL
116 /* our ALE is AD21 */
117 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
118 /* our CLE is AD22 */
119 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
120 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
121 #endif
122
123 /* JFFS2 */
124 #ifdef CONFIG_CMD_JFFS2
125 #define CONFIG_JFFS2_CMDLINE
126 #define CONFIG_JFFS2_NAND
127 #endif
128
129 /* Ethernet */
130 #define CONFIG_NET_RETRY_COUNT 20
131 #define CONFIG_MACB
132 #define CONFIG_RMII
133 #define CONFIG_PHY_ID 0
134 #define CONFIG_MACB_SEARCH_PHY
135
136 /* MMC */
137 #ifdef CONFIG_CMD_MMC
138 #define CONFIG_MMC
139 #define CONFIG_GENERIC_MMC
140 #define CONFIG_GENERIC_ATMEL_MCI
141 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
142 #endif
143
144 /* USB */
145 #ifdef CONFIG_CMD_USB
146 #define CONFIG_USB_ATMEL
147 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
148 #define CONFIG_USB_OHCI_NEW
149 #define CONFIG_SYS_USB_OHCI_CPU_INIT
150 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
151 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
152 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
153 #define CONFIG_USB_STORAGE
154 #endif
155
156 /* RTC */
157 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
158 #define CONFIG_RTC_PCF8563
159 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
160 #endif
161
162 /* I2C */
163 #define CONFIG_SYS_MAX_I2C_BUS 1
164
165 #define CONFIG_SYS_I2C
166 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
167 #define CONFIG_SYS_I2C_SOFT_SPEED 100000
168 #define CONFIG_SYS_I2C_SOFT_SLAVE 0
169
170 #define I2C_SOFT_DECLARATIONS
171
172 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24
173 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23
174
175 #define I2C_INIT { \
176 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
177 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
178 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
179 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
180 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
181 }
182
183 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
184 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
185 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
186 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
187 #define I2C_DELAY udelay(100)
188 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
189
190 /* DHCP/BOOTP options */
191 #ifdef CONFIG_CMD_DHCP
192 #define CONFIG_BOOTP_BOOTFILESIZE
193 #define CONFIG_BOOTP_BOOTPATH
194 #define CONFIG_BOOTP_GATEWAY
195 #define CONFIG_BOOTP_HOSTNAME
196 #define CONFIG_SYS_AUTOLOAD "n"
197 #endif
198
199 /* File systems */
200 #define CONFIG_MTD_DEVICE
201 #define CONFIG_MTD_PARTITIONS
202 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
203 #define MTDIDS_DEFAULT "nand0=atmel_nand"
204 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
205 #endif
206 #if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
207 defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
208 #define CONFIG_DOS_PARTITION
209 #endif
210 #define CONFIG_LZO
211 #define CONFIG_RBTREE
212
213 /* Boot command */
214 #define CONFIG_BOOTDELAY 3
215 #define CONFIG_CMDLINE_TAG
216 #define CONFIG_SETUP_MEMORY_TAGS
217 #define CONFIG_INITRD_TAG
218 #define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
219 #if defined(CONFIG_CMD_NAND)
220 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
221 "root=/dev/mtdblock0 " \
222 MTDPARTS_DEFAULT \
223 " rw rootfstype=jffs2"
224 #endif
225
226 /* Misc. u-boot settings */
227 #define CONFIG_SYS_CBSIZE 256
228 #define CONFIG_SYS_MAXARGS 16
229 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
230 + sizeof(CONFIG_SYS_PROMPT))
231 #define CONFIG_SYS_LONGHELP
232 #define CONFIG_CMDLINE_EDITING
233
234 #endif