include/configs/ethernut5.h

   1 /*
   2  * (C) Copyright 2011
   3  * egnite GmbH <info@egnite.de>
   4  *
   5  * Configuation settings for Ethernut 5 with AT91SAM9XE.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <asm/hardware.h>
  14
  15
  16 /* The first stage boot loader expects u-boot running at this address. */
  17 #define CONFIG_SYS_TEXT_BASE    0x27000000      /* 16MB available */
  18
  19 /* The first stage boot loader takes care of low level initialization. */
  20 #define CONFIG_SKIP_LOWLEVEL_INIT
  21
  22 /* Set our official architecture number. */
  23 #define MACH_TYPE_ETHERNUT5 1971
  24 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
  25
  26 /* CPU information */
  27 #define CONFIG_DISPLAY_CPUINFO          /* Display at console. */
  28 #define CONFIG_ARCH_CPU_INIT
  29
  30 /* ARM asynchronous clock */
  31 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768   /* slow clock xtal */
  32 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000 /* 18.432 MHz crystal */
  33
  34 /* 32kB internal SRAM */
  35 #define CONFIG_SRAM_BASE        0x00300000 /*AT91SAM9XE_SRAM_BASE */
  36 #define CONFIG_SRAM_SIZE        (32 << 10)
  37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
  38                                 GENERATED_GBL_DATA_SIZE)
  39
  40 /* 128MB SDRAM in 1 bank */
  41 #define CONFIG_NR_DRAM_BANKS            1
  42 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  43 #define CONFIG_SYS_SDRAM_SIZE           (128 << 20)
  44 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE
  45 #define CONFIG_LOADADDR                 CONFIG_SYS_LOAD_ADDR
  46 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (1 << 20))
  47 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  48 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE \
  49                                         - CONFIG_SYS_MALLOC_LEN)
  50
  51 /* 512kB on-chip NOR flash */
  52 # define CONFIG_SYS_MAX_FLASH_BANKS     1
  53 # define CONFIG_SYS_FLASH_BASE          0x00200000 /* AT91SAM9XE_FLASH_BASE */
  54 # define CONFIG_AT91_EFLASH
  55 # define CONFIG_SYS_MAX_FLASH_SECT      32
  56 # define CONFIG_SYS_FLASH_PROTECTION    /* First stage loader in sector 0 */
  57 # define CONFIG_EFLASH_PROTSECTORS      1
  58
  59 /* 512kB DataFlash at NPCS0 */
  60 #define CONFIG_SYS_MAX_DATAFLASH_BANKS  1
  61 #define CONFIG_HAS_DATAFLASH
  62 #define CONFIG_SPI_FLASH_ATMEL
  63 #define CONFIG_ATMEL_DATAFLASH_SPI
  64 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000
  65 #define DATAFLASH_TCSS                  (0x1a << 16)
  66 #define DATAFLASH_TCHS                  (0x1 << 24)
  67
  68 #define CONFIG_ENV_IS_IN_SPI_FLASH
  69 #define CONFIG_ENV_OFFSET               0x3DE000
  70 #define CONFIG_ENV_SECT_SIZE            (132 << 10)
  71 #define CONFIG_ENV_SIZE                 CONFIG_ENV_SECT_SIZE
  72 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
  73                                         + CONFIG_ENV_OFFSET)
  74 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
  75                                         + 0x042000)
  76
  77 /* SPI */
  78 #define CONFIG_ATMEL_SPI
  79 #define AT91_SPI_CLK                    15000000
  80
  81 /* Serial port */
  82 #define CONFIG_ATMEL_USART
  83 #define CONFIG_USART3                   /* USART 3 is DBGU */
  84 #define CONFIG_BAUDRATE                 115200
  85 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  86 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  87
  88 /* Misc. hardware drivers */
  89 #define CONFIG_AT91_GPIO
  90
  91 /* Command line configuration */
  92 #define CONFIG_CMD_JFFS2
  93 #define CONFIG_CMD_MII
  94 #define CONFIG_CMD_MTDPARTS
  95 #define CONFIG_CMD_NAND
  96 #define CONFIG_CMD_SPI
  97
  98 #ifndef MINIMAL_LOADER
  99 #define CONFIG_CMD_ASKENV
 100 #define CONFIG_CMD_BSP
 101 #define CONFIG_CMD_CACHE
 102 #define CONFIG_CMD_CDP
 103 #define CONFIG_CMD_DATE
 104 #define CONFIG_CMD_DHCP
 105 #define CONFIG_CMD_DNS
 106 #define CONFIG_CMD_EXT2
 107 #define CONFIG_CMD_FAT
 108 #define CONFIG_CMD_I2C
 109 #define CONFIG_CMD_MMC
 110 #define CONFIG_CMD_PING
 111 #define CONFIG_CMD_RARP
 112 #define CONFIG_CMD_REISER
 113 #define CONFIG_CMD_SAVES
 114 #define CONFIG_CMD_SF
 115 #define CONFIG_CMD_SNTP
 116 #define CONFIG_CMD_UBI
 117 #define CONFIG_CMD_UBIFS
 118 #define CONFIG_CMD_UNZIP
 119 #define CONFIG_CMD_USB
 120 #endif
 121
 122 /* NAND flash */
 123 #ifdef CONFIG_CMD_NAND
 124 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 125 #define CONFIG_SYS_NAND_BASE            0x40000000
 126 #define CONFIG_SYS_NAND_DBW_8
 127 #define CONFIG_NAND_ATMEL
 128 /* our ALE is AD21 */
 129 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
 130 /* our CLE is AD22 */
 131 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
 132 #define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
 133 #endif
 134
 135 /* JFFS2 */
 136 #ifdef CONFIG_CMD_JFFS2
 137 #define CONFIG_JFFS2_CMDLINE
 138 #define CONFIG_JFFS2_NAND
 139 #endif
 140
 141 /* Ethernet */
 142 #define CONFIG_NET_RETRY_COUNT          20
 143 #define CONFIG_MACB
 144 #define CONFIG_RMII
 145 #define CONFIG_PHY_ID                   0
 146 #define CONFIG_MACB_SEARCH_PHY
 147
 148 /* MMC */
 149 #ifdef CONFIG_CMD_MMC
 150 #define CONFIG_MMC
 151 #define CONFIG_GENERIC_MMC
 152 #define CONFIG_GENERIC_ATMEL_MCI
 153 #define CONFIG_SYS_MMC_CD_PIN           AT91_PIO_PORTC, 8
 154 #endif
 155
 156 /* USB */
 157 #ifdef CONFIG_CMD_USB
 158 #define CONFIG_USB_ATMEL
 159 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 160 #define CONFIG_USB_OHCI_NEW
 161 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 162 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00500000
 163 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "host"
 164 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 165 #define CONFIG_USB_STORAGE
 166 #endif
 167
 168 /* RTC */
 169 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
 170 #define CONFIG_RTC_PCF8563
 171 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 172 #endif
 173
 174 /* I2C */
 175 #define CONFIG_SYS_MAX_I2C_BUS  1
 176
 177 #define CONFIG_SYS_I2C
 178 #define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 179 #define CONFIG_SYS_I2C_SOFT_SPEED       100000
 180 #define CONFIG_SYS_I2C_SOFT_SLAVE       0
 181
 182 #define I2C_SOFT_DECLARATIONS
 183
 184 #define GPIO_I2C_SCL            AT91_PIO_PORTA, 24
 185 #define GPIO_I2C_SDA            AT91_PIO_PORTA, 23
 186
 187 #define I2C_INIT { \
 188         at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
 189         at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
 190         at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
 191         at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
 192         at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
 193 }
 194
 195 #define I2C_ACTIVE      at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
 196 #define I2C_TRISTATE    at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
 197 #define I2C_SCL(bit)    at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
 198 #define I2C_SDA(bit)    at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
 199 #define I2C_DELAY       udelay(100)
 200 #define I2C_READ        at91_get_pio_value(AT91_PIO_PORTA, 23)
 201
 202 /* DHCP/BOOTP options */
 203 #ifdef CONFIG_CMD_DHCP
 204 #define CONFIG_BOOTP_BOOTFILESIZE
 205 #define CONFIG_BOOTP_BOOTPATH
 206 #define CONFIG_BOOTP_GATEWAY
 207 #define CONFIG_BOOTP_HOSTNAME
 208 #define CONFIG_SYS_AUTOLOAD     "n"
 209 #endif
 210
 211 /* File systems */
 212 #define CONFIG_MTD_DEVICE
 213 #define CONFIG_MTD_PARTITIONS
 214 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
 215 #define MTDIDS_DEFAULT          "nand0=atmel_nand"
 216 #define MTDPARTS_DEFAULT        "mtdparts=atmel_nand:-(root)"
 217 #endif
 218 #if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
 219         defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
 220 #define CONFIG_DOS_PARTITION
 221 #endif
 222 #define CONFIG_LZO
 223 #define CONFIG_RBTREE
 224
 225 /* Boot command */
 226 #define CONFIG_BOOTDELAY        3
 227 #define CONFIG_CMDLINE_TAG
 228 #define CONFIG_SETUP_MEMORY_TAGS
 229 #define CONFIG_INITRD_TAG
 230 #define CONFIG_BOOTCOMMAND      "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
 231 #if defined(CONFIG_CMD_NAND)
 232 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 233                                 "root=/dev/mtdblock0 " \
 234                                 MTDPARTS_DEFAULT \
 235                                 " rw rootfstype=jffs2"
 236 #endif
 237
 238 /* Misc. u-boot settings */
 239 #define CONFIG_SYS_HUSH_PARSER
 240 #define CONFIG_SYS_CBSIZE               256
 241 #define CONFIG_SYS_MAXARGS              16
 242 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + 16 \
 243                                         + sizeof(CONFIG_SYS_PROMPT))
 244 #define CONFIG_SYS_LONGHELP
 245 #define CONFIG_CMDLINE_EDITING
 246
 247 #endif