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Convert CONFIG_CMD_REISER to Kconfig
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1 /*
2 * (C) Copyright 2011
3 * egnite GmbH <info@egnite.de>
4 *
5 * Configuation settings for Ethernut 5 with AT91SAM9XE.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #include <asm/hardware.h>
14
15 /* The first stage boot loader expects u-boot running at this address. */
16 #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
17
18 /* The first stage boot loader takes care of low level initialization. */
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20
21 /* Set our official architecture number. */
22 #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
23
24 /* CPU information */
25 #define CONFIG_ARCH_CPU_INIT
26
27 /* ARM asynchronous clock */
28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
29 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
30
31 /* 32kB internal SRAM */
32 #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
33 #define CONFIG_SRAM_SIZE (32 << 10)
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
35 GENERATED_GBL_DATA_SIZE)
36
37 /* 128MB SDRAM in 1 bank */
38 #define CONFIG_NR_DRAM_BANKS 1
39 #define CONFIG_SYS_SDRAM_BASE 0x20000000
40 #define CONFIG_SYS_SDRAM_SIZE (128 << 20)
41 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
42 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
44 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
45 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
46 - CONFIG_SYS_MALLOC_LEN)
47
48 /* 512kB on-chip NOR flash */
49 # define CONFIG_SYS_MAX_FLASH_BANKS 1
50 # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
51 # define CONFIG_AT91_EFLASH
52 # define CONFIG_SYS_MAX_FLASH_SECT 32
53 # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */
54 # define CONFIG_EFLASH_PROTSECTORS 1
55
56
57 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
58 #define CONFIG_ENV_OFFSET 0x3DE000
59 #define CONFIG_ENV_SIZE (132 << 10)
60 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
61 #define CONFIG_ENV_SPI_MAX_HZ 15000000
62
63 #ifndef MINIMAL_LOADER
64 #define CONFIG_CMD_SAVES
65 #endif
66
67 /* NAND flash */
68 #ifdef CONFIG_CMD_NAND
69 #define CONFIG_SYS_MAX_NAND_DEVICE 1
70 #define CONFIG_SYS_NAND_BASE 0x40000000
71 #define CONFIG_SYS_NAND_DBW_8
72 #define CONFIG_NAND_ATMEL
73 /* our ALE is AD21 */
74 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
75 /* our CLE is AD22 */
76 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
77 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
78 #endif
79
80 /* JFFS2 */
81 #ifdef CONFIG_CMD_JFFS2
82 #define CONFIG_JFFS2_CMDLINE
83 #define CONFIG_JFFS2_NAND
84 #endif
85
86 /* Ethernet */
87 #define CONFIG_NET_RETRY_COUNT 20
88 #define CONFIG_MACB
89 #define CONFIG_RMII
90 #define CONFIG_PHY_ID 0
91 #define CONFIG_MACB_SEARCH_PHY
92
93 /* MMC */
94 #ifdef CONFIG_CMD_MMC
95 #define CONFIG_GENERIC_ATMEL_MCI
96 #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
97 #endif
98
99 /* USB */
100 #ifdef CONFIG_CMD_USB
101 #define CONFIG_USB_ATMEL
102 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
103 #define CONFIG_USB_OHCI_NEW
104 #define CONFIG_SYS_USB_OHCI_CPU_INIT
105 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
106 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
107 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
108 #endif
109
110 /* RTC */
111 #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
112 #define CONFIG_RTC_PCF8563
113 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
114 #endif
115
116 /* I2C */
117 #define CONFIG_SYS_MAX_I2C_BUS 1
118
119 #define CONFIG_SYS_I2C
120 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
121 #define CONFIG_SYS_I2C_SOFT_SPEED 100000
122 #define CONFIG_SYS_I2C_SOFT_SLAVE 0
123
124 #define I2C_SOFT_DECLARATIONS
125
126 #define GPIO_I2C_SCL AT91_PIO_PORTA, 24
127 #define GPIO_I2C_SDA AT91_PIO_PORTA, 23
128
129 #define I2C_INIT { \
130 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
131 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
132 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
133 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
134 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
135 }
136
137 #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
138 #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
139 #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
140 #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
141 #define I2C_DELAY udelay(100)
142 #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
143
144 /* DHCP/BOOTP options */
145 #ifdef CONFIG_CMD_DHCP
146 #define CONFIG_BOOTP_BOOTFILESIZE
147 #define CONFIG_BOOTP_BOOTPATH
148 #define CONFIG_BOOTP_GATEWAY
149 #define CONFIG_BOOTP_HOSTNAME
150 #define CONFIG_SYS_AUTOLOAD "n"
151 #endif
152
153 /* File systems */
154 #define CONFIG_MTD_DEVICE
155 #define CONFIG_MTD_PARTITIONS
156 #if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
157 #define MTDIDS_DEFAULT "nand0=atmel_nand"
158 #define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)"
159 #endif
160
161 /* Boot command */
162 #define CONFIG_CMDLINE_TAG
163 #define CONFIG_SETUP_MEMORY_TAGS
164 #define CONFIG_INITRD_TAG
165 #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
166 "sf read 0x22000000 0xc6000 0x294000; " \
167 "bootm 0x22000000"
168 #if defined(CONFIG_CMD_NAND)
169 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
170 "root=/dev/mtdblock0 " \
171 MTDPARTS_DEFAULT \
172 " rw rootfstype=jffs2"
173 #endif
174
175 /* Misc. u-boot settings */
176 #define CONFIG_SYS_CBSIZE 256
177 #define CONFIG_SYS_MAXARGS 16
178 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \
179 + sizeof(CONFIG_SYS_PROMPT))
180 #define CONFIG_SYS_LONGHELP
181 #define CONFIG_CMDLINE_EDITING
182
183 #endif