include/configs/exynos5-common.h

   1 /*
   2  * Copyright (C) 2013 Samsung Electronics
   3  *
   4  * Configuration settings for the SAMSUNG EXYNOS5 board.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_EXYNOS5_COMMON_H
  10 #define __CONFIG_EXYNOS5_COMMON_H
  11
  12 #define CONFIG_EXYNOS5                  /* Exynos5 Family */
  13
  14 #include "exynos-common.h"
  15
  16 #define CONFIG_EXYNOS_SPL
  17
  18 #ifdef FTRACE
  19 #define CONFIG_TRACE
  20 #define CONFIG_CMD_TRACE
  21 #define CONFIG_TRACE_BUFFER_SIZE        (16 << 20)
  22 #define CONFIG_TRACE_EARLY_SIZE         (8 << 20)
  23 #define CONFIG_TRACE_EARLY
  24 #define CONFIG_TRACE_EARLY_ADDR         0x50000000
  25 #endif
  26
  27 /* Enable ACE acceleration for SHA1 and SHA256 */
  28 #define CONFIG_EXYNOS_ACE_SHA
  29 #define CONFIG_SHA_HW_ACCEL
  30
  31 /* Power Down Modes */
  32 #define S5P_CHECK_SLEEP                 0x00000BAD
  33 #define S5P_CHECK_DIDLE                 0xBAD00000
  34 #define S5P_CHECK_LPA                   0xABAD0000
  35
  36 /* Offset for inform registers */
  37 #define INFORM0_OFFSET                  0x800
  38 #define INFORM1_OFFSET                  0x804
  39 #define INFORM2_OFFSET                  0x808
  40 #define INFORM3_OFFSET                  0x80c
  41
  42 /* select serial console configuration */
  43 #define CONFIG_BAUDRATE                 115200
  44 #define EXYNOS5_DEFAULT_UART_OFFSET     0x010000
  45 #define CONFIG_SILENT_CONSOLE
  46 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  47 #define CONFIG_CONSOLE_MUX
  48
  49 #define CONFIG_CMD_HASH
  50
  51 /* Thermal Management Unit */
  52 #define CONFIG_EXYNOS_TMU
  53 #define CONFIG_CMD_DTT
  54 #define CONFIG_TMU_CMD_DTT
  55
  56 /* MMC SPL */
  57 #define COPY_BL2_FNPTR_ADDR     0x02020030
  58 #define CONFIG_SUPPORT_EMMC_BOOT
  59
  60 /* specific .lds file */
  61 #define CONFIG_SPL_LDSCRIPT     "board/samsung/common/exynos-uboot-spl.lds"
  62
  63 /* Boot Argument Buffer Size */
  64 /* memtest works on */
  65 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  66 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
  67 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  68
  69 #define CONFIG_RD_LVL
  70
  71 #define PHYS_SDRAM_1            CONFIG_SYS_SDRAM_BASE
  72 #define PHYS_SDRAM_1_SIZE       SDRAM_BANK_SIZE
  73 #define PHYS_SDRAM_2            (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
  74 #define PHYS_SDRAM_2_SIZE       SDRAM_BANK_SIZE
  75 #define PHYS_SDRAM_3            (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
  76 #define PHYS_SDRAM_3_SIZE       SDRAM_BANK_SIZE
  77 #define PHYS_SDRAM_4            (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
  78 #define PHYS_SDRAM_4_SIZE       SDRAM_BANK_SIZE
  79 #define PHYS_SDRAM_5            (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
  80 #define PHYS_SDRAM_5_SIZE       SDRAM_BANK_SIZE
  81 #define PHYS_SDRAM_6            (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
  82 #define PHYS_SDRAM_6_SIZE       SDRAM_BANK_SIZE
  83 #define PHYS_SDRAM_7            (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
  84 #define PHYS_SDRAM_7_SIZE       SDRAM_BANK_SIZE
  85 #define PHYS_SDRAM_8            (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
  86 #define PHYS_SDRAM_8_SIZE       SDRAM_BANK_SIZE
  87
  88 #define CONFIG_SYS_MONITOR_BASE 0x00000000
  89
  90 #define CONFIG_SYS_MMC_ENV_DEV          0
  91
  92 #define CONFIG_SECURE_BL1_ONLY
  93
  94 /* Secure FW size configuration */
  95 #ifdef CONFIG_SECURE_BL1_ONLY
  96 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
  97 #else
  98 #define CONFIG_SEC_FW_SIZE 0
  99 #endif
 100
 101 /* Configuration of BL1, BL2, ENV Blocks on mmc */
 102 #define CONFIG_RES_BLOCK_SIZE   (512)
 103 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
 104 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
 105 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
 106
 107 #define CONFIG_BL1_OFFSET       (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
 108 #define CONFIG_BL2_OFFSET       (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
 109
 110 /* U-Boot copy size from boot Media to DRAM.*/
 111 #define BL2_START_OFFSET        (CONFIG_BL2_OFFSET/512)
 112 #define BL2_SIZE_BLOC_COUNT     (CONFIG_BL2_SIZE/512)
 113
 114 #define EXYNOS_COPY_SPI_FNPTR_ADDR      0x02020058
 115 #define SPI_FLASH_UBOOT_POS     (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
 116
 117 /* I2C */
 118 #define CONFIG_SYS_I2C_S3C24X0
 119 #define CONFIG_SYS_I2C_S3C24X0_SPEED    100000          /* 100 Kbps */
 120 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
 121
 122 /* SPI */
 123 #ifdef CONFIG_SPI_FLASH
 124 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 125 #define CONFIG_SF_DEFAULT_SPEED         50000000
 126 #endif
 127
 128 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 129 #define CONFIG_ENV_SPI_MODE     SPI_MODE_0
 130 #define CONFIG_ENV_SECT_SIZE    CONFIG_ENV_SIZE
 131 #define CONFIG_ENV_SPI_BUS      1
 132 #define CONFIG_ENV_SPI_MAX_HZ   50000000
 133 #endif
 134
 135 /* Ethernet Controllor Driver */
 136 #ifdef CONFIG_CMD_NET
 137 #define CONFIG_SMC911X
 138 #define CONFIG_SMC911X_BASE             0x5000000
 139 #define CONFIG_SMC911X_16_BIT
 140 #define CONFIG_ENV_SROM_BANK            1
 141 #endif /*CONFIG_CMD_NET*/
 142
 143 /* SHA hashing */
 144 #define CONFIG_CMD_HASH
 145 #define CONFIG_HASH_VERIFY
 146 #define CONFIG_SHA1
 147 #define CONFIG_SHA256
 148
 149 /* Enable Time Command */
 150
 151 /* USB */
 152 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      3
 153 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 154
 155 #define CONFIG_USB_HOST_ETHER
 156 #define CONFIG_USB_ETHER_ASIX
 157 #define CONFIG_USB_ETHER_SMSC95XX
 158 #define CONFIG_USB_ETHER_RTL8152
 159
 160 /* USB boot mode */
 161 #define CONFIG_USB_BOOTING
 162 #define EXYNOS_COPY_USB_FNPTR_ADDR      0x02020070
 163 #define EXYNOS_USB_SECONDARY_BOOT       0xfeed0002
 164 #define EXYNOS_IRAM_SECONDARY_BASE      0x02020018
 165
 166 #define BOOT_TARGET_DEVICES(func) \
 167         func(MMC, mmc, 1) \
 168         func(MMC, mmc, 0) \
 169         func(PXE, pxe, na) \
 170         func(DHCP, dhcp, na)
 171
 172 #include <config_distro_bootcmd.h>
 173
 174 #ifndef MEM_LAYOUT_ENV_SETTINGS
 175 /* 2GB RAM, bootm size of 256M, load scripts after that */
 176 #define MEM_LAYOUT_ENV_SETTINGS \
 177         "bootm_size=0x10000000\0" \
 178         "kernel_addr_r=0x42000000\0" \
 179         "fdt_addr_r=0x43000000\0" \
 180         "ramdisk_addr_r=0x43300000\0" \
 181         "scriptaddr=0x50000000\0" \
 182         "pxefile_addr_r=0x51000000\0"
 183 #endif
 184
 185 #ifndef EXYNOS_DEVICE_SETTINGS
 186 #define EXYNOS_DEVICE_SETTINGS \
 187         "stdin=serial\0" \
 188         "stdout=serial\0" \
 189         "stderr=serial\0"
 190 #endif
 191
 192 #ifndef EXYNOS_FDTFILE_SETTING
 193 #define EXYNOS_FDTFILE_SETTING
 194 #endif
 195
 196 #define CONFIG_EXTRA_ENV_SETTINGS \
 197         EXYNOS_DEVICE_SETTINGS \
 198         EXYNOS_FDTFILE_SETTING \
 199         MEM_LAYOUT_ENV_SETTINGS \
 200         BOOTENV
 201
 202 #endif  /* __CONFIG_EXYNOS5_COMMON_H */