include/configs/exynos7420-common.h

   1 /*
   2  * Configuration settings for the Espresso7420 board.
   3  * Copyright (C) 2016 Samsung Electronics
   4  * Thomas Abraham <thomas.ab@samsung.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_EXYNOS7420_COMMON_H
  10 #define __CONFIG_EXYNOS7420_COMMON_H
  11
  12 /* High Level Configuration Options */
  13 #define CONFIG_SAMSUNG                  /* in a SAMSUNG core */
  14 #define CONFIG_EXYNOS7420               /* Exynos7 Family */
  15 #define CONFIG_S5P
  16
  17 #include <asm/arch/cpu.h>               /* get chip and board defs */
  18 #include <linux/sizes.h>
  19
  20 #define CONFIG_ARCH_CPU_INIT
  21
  22 /* Size of malloc() pool before and after relocation */
  23 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (80 << 20))
  24
  25 /* Miscellaneous configurable options */
  26 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
  27 #define CONFIG_SYS_PBSIZE               1024    /* Print Buffer Size */
  28
  29 /* Boot Argument Buffer Size */
  30 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  31
  32 /* select serial console configuration */
  33
  34 /* Timer input clock frequency */
  35 #define COUNTER_FREQUENCY               24000000
  36
  37 /* Device Tree */
  38 #define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
  39
  40 /* IRAM Layout */
  41 #define CONFIG_IRAM_BASE                0x02100000
  42 #define CONFIG_IRAM_SIZE                0x58000
  43 #define CONFIG_IRAM_END                 (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
  44 #define CPU_RELEASE_ADDR                secondary_boot_addr
  45
  46 /* select serial console configuration */
  47
  48 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  49
  50 #define PHYS_SDRAM_1            CONFIG_SYS_SDRAM_BASE
  51 #define PHYS_SDRAM_1_SIZE       SDRAM_BANK_SIZE
  52 #define PHYS_SDRAM_2            (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
  53 #define PHYS_SDRAM_2_SIZE       SDRAM_BANK_SIZE
  54 #define PHYS_SDRAM_3            (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
  55 #define PHYS_SDRAM_3_SIZE       SDRAM_BANK_SIZE
  56 #define PHYS_SDRAM_4            (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
  57 #define PHYS_SDRAM_4_SIZE       SDRAM_BANK_SIZE
  58 #define PHYS_SDRAM_5            (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
  59 #define PHYS_SDRAM_5_SIZE       SDRAM_BANK_SIZE
  60 #define PHYS_SDRAM_6            (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
  61 #define PHYS_SDRAM_6_SIZE       SDRAM_BANK_SIZE
  62 #define PHYS_SDRAM_7            (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
  63 #define PHYS_SDRAM_7_SIZE       SDRAM_BANK_SIZE
  64 #define PHYS_SDRAM_8            (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
  65 #define PHYS_SDRAM_8_SIZE       SDRAM_BANK_SIZE
  66
  67 /* Configuration of ENV Blocks */
  68 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
  69
  70 #define BOOT_TARGET_DEVICES(func) \
  71         func(MMC, mmc, 1) \
  72         func(MMC, mmc, 0) \
  73
  74 #ifndef MEM_LAYOUT_ENV_SETTINGS
  75 #define MEM_LAYOUT_ENV_SETTINGS \
  76         "bootm_size=0x10000000\0" \
  77         "kernel_addr_r=0x42000000\0" \
  78         "fdt_addr_r=0x43000000\0" \
  79         "ramdisk_addr_r=0x43300000\0" \
  80         "scriptaddr=0x50000000\0" \
  81         "pxefile_addr_r=0x51000000\0"
  82 #endif
  83
  84 #ifndef EXYNOS_DEVICE_SETTINGS
  85 #define EXYNOS_DEVICE_SETTINGS \
  86         "stdin=serial\0" \
  87         "stdout=serial\0" \
  88         "stderr=serial\0"
  89 #endif
  90
  91 #ifndef EXYNOS_FDTFILE_SETTING
  92 #define EXYNOS_FDTFILE_SETTING
  93 #endif
  94
  95 #define CONFIG_EXTRA_ENV_SETTINGS \
  96         EXYNOS_DEVICE_SETTINGS \
  97         EXYNOS_FDTFILE_SETTING \
  98         MEM_LAYOUT_ENV_SETTINGS
  99
 100 #endif  /* __CONFIG_EXYNOS7420_COMMON_H */