include/configs/gw8260.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2001
  10  * Advent Networks, Inc. <http://www.adventnetworks.com>
  11  * Jay Monkman <jmonkman@adventnetworks.com>
  12  *
  13  * (C) Copyright 2001
  14  * Advent Networks, Inc. <http://www.adventnetworks.com>
  15  * Oliver Brown <obrown@adventnetworks.com>
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35
  36 /*********************************************************************/
  37 /* DESCRIPTION:
  38  *   This file contains the board configuartion for the GW8260 board.
  39  *
  40  * MODULE DEPENDENCY:
  41  *   None
  42  *
  43  * RESTRICTIONS/LIMITATIONS:
  44  *   None
  45  *
  46  * Copyright (c) 2001, Advent Networks, Inc.
  47  */
  48 /*********************************************************************/
  49
  50 #ifndef __CONFIG_H
  51 #define __CONFIG_H
  52
  53 /* Enable debug prints */
  54 #undef DEBUG                  /* General debug */
  55 #undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
  56
  57 /* What is the oscillator's (UX2) frequency in Hz? */
  58 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  59
  60 /*-----------------------------------------------------------------------
  61  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  62  *-----------------------------------------------------------------------
  63  * What should MODCK_H be? It is dependent on the oscillator
  64  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  65  * Here are some example values (all frequencies are in MHz):
  66  *
  67  * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
  68  * -------   ----------  ---    ---    ----  -----  -----  -----
  69  * 0x5       0x5     66 133     133    Open  Close  Open
  70  * 0x5       0x6     66 133     166    Open  Open   Close
  71  * 0x5       0x7     66 133     200    Open  Open   Open
  72  * 0x6       0x0     66 133     233    Close Close  Close
  73  * 0x6       0x1     66 133     266    Close Close  Open
  74  * 0x6       0x2     66 133     300    Close Open   Close
  75  */
  76 #define CFG_SBC_MODCK_H 0x05
  77
  78 /* Define this if you want to boot from 0x00000100. If you don't define
  79  * this, you will need to program the bootloader to 0xfff00000, and
  80  * get the hardware reset config words at 0xfe000000. The simplest
  81  * way to do that is to program the bootloader at both addresses.
  82  * It is suggested that you just let U-Boot live at 0x00000000.
  83  */
  84 #define CFG_SBC_BOOT_LOW 1
  85
  86 /* What should the base address of the main FLASH be and how big is
  87  * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
  88  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  89  * this to be the SIMM.
  90  */
  91 #define CFG_FLASH0_BASE 0x40000000
  92 #define CFG_FLASH0_SIZE 8
  93
  94 /* Define CFG_FLASH_CHECKSUM to enable flash checksum during boot.
  95  * Note: the 'flashchecksum' environment variable must also be set to 'y'.
  96  */
  97 #define CFG_FLASH_CHECKSUM
  98
  99 /* What should be the base address of SDRAM DIMM and how big is
 100  * it (in Mbytes)?
 101  */
 102 #define CFG_SDRAM0_BASE 0x00000000
 103 #define CFG_SDRAM0_SIZE 64
 104
 105 /*
 106  * DRAM tests
 107  *   CFG_DRAM_TEST - enables the following tests.
 108  *
 109  *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
 110  *                        Environment variable 'test_dram_data' must be
 111  *                        set to 'y'.
 112  *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
 113  *                        addressable. Environment variable
 114  *                        'test_dram_address' must be set to 'y'.
 115  *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
 116  *                        This test takes about 6 minutes to test 64 MB.
 117  *                        Environment variable 'test_dram_walk' must be
 118  *                        set to 'y'.
 119  */
 120 #define CFG_DRAM_TEST
 121 #if defined(CFG_DRAM_TEST)
 122 #define CFG_DRAM_TEST_DATA
 123 #define CFG_DRAM_TEST_ADDRESS
 124 #define CFG_DRAM_TEST_WALK
 125 #endif /* CFG_DRAM_TEST */
 126
 127 /*
 128  * GW8260 with 16 MB DIMM:
 129  *
 130  *     0x0000 0000     Exception Vector code, 8k
 131  *           :
 132  *     0x0000 1FFF
 133  *     0x0000 2000     Free for Application Use
 134  *           :
 135  *           :
 136  *
 137  *           :
 138  *           :
 139  *     0x00F5 FF30     Monitor Stack (Growing downward)
 140  *                     Monitor Stack Buffer (0x80)
 141  *     0x00F5 FFB0     Board Info Data
 142  *     0x00F6 0000     Malloc Arena
 143  *           :          CFG_ENV_SECT_SIZE, 256k
 144  *           :          CFG_MALLOC_LEN,    128k
 145  *     0x00FC 0000     RAM Copy of Monitor Code
 146  *           :              CFG_MONITOR_LEN,   256k
 147  *     0x00FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
 148  */
 149
 150 /*
 151  * GW8260 with 64 MB DIMM:
 152  *
 153  *     0x0000 0000     Exception Vector code, 8k
 154  *           :
 155  *     0x0000 1FFF
 156  *     0x0000 2000     Free for Application Use
 157  *           :
 158  *           :
 159  *
 160  *           :
 161  *           :
 162  *     0x03F5 FF30     Monitor Stack (Growing downward)
 163  *                     Monitor Stack Buffer (0x80)
 164  *     0x03F5 FFB0     Board Info Data
 165  *     0x03F6 0000     Malloc Arena
 166  *           :          CFG_ENV_SECT_SIZE, 256k
 167  *           :          CFG_MALLOC_LEN,    128k
 168  *     0x03FC 0000     RAM Copy of Monitor Code
 169  *           :              CFG_MONITOR_LEN,   256k
 170  *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
 171  */
 172
 173
 174 /*
 175  * select serial console configuration
 176  *
 177  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 178  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 179  * for SCC).
 180  *
 181  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 182  * defined elsewhere.
 183  */
 184 #define CONFIG_CONS_ON_SMC  1   /* define if console on SMC */
 185 #undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
 186 #undef  CONFIG_CONS_NONE        /* define if console on neither */
 187 #define CONFIG_CONS_INDEX   1   /* which SMC/SCC channel for console */
 188
 189 /*
 190  * select ethernet configuration
 191  *
 192  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 193  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 194  * for FCC)
 195  *
 196  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 197  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 198  * from CONFIG_COMMANDS to remove support for networking.
 199  */
 200
 201 #undef  CONFIG_ETHER_ON_SCC
 202 #define CONFIG_ETHER_ON_FCC
 203 #undef  CONFIG_ETHER_NONE       /* define if ethernet on neither */
 204
 205 #ifdef  CONFIG_ETHER_ON_SCC
 206 #define CONFIG_ETHER_INDEX  1   /* which SCC/FCC channel for ethernet */
 207 #endif  /* CONFIG_ETHER_ON_SCC */
 208
 209 #ifdef  CONFIG_ETHER_ON_FCC
 210 #define CONFIG_ETHER_INDEX  2   /* which SCC/FCC channel for ethernet */
 211 #define CONFIG_MII              /* MII PHY management           */
 212 #define CONFIG_BITBANGMII       /* bit-bang MII PHY management  */
 213 /*
 214  * Port pins used for bit-banged MII communictions (if applicable).
 215  */
 216 #define MDIO_PORT   2       /* Port C */
 217 #define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
 218 #define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
 219 #define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
 220
 221 #define MDIO(bit)   if(bit) iop->pdat |=  0x00400000; \
 222             else            iop->pdat &= ~0x00400000
 223
 224 #define MDC(bit)    if(bit) iop->pdat |=  0x00200000; \
 225             else    iop->pdat &= ~0x00200000
 226
 227 #define MIIDELAY    udelay(1)
 228 #endif  /* CONFIG_ETHER_ON_FCC */
 229
 230 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 231
 232 /*
 233  * - Rx-CLK is CLK13
 234  * - Tx-CLK is CLK14
 235  * - Select bus for bd/buffers (see 28-13)
 236  * - Enable Full Duplex in FSMR
 237  */
 238 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 239 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 240 # define CFG_CPMFCR_RAMTYPE     0
 241 # define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
 242
 243 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 244
 245 /*
 246  * - Rx-CLK is CLK15
 247  * - Tx-CLK is CLK16
 248  * - Select bus for bd/buffers (see 28-13)
 249  * - Enable Full Duplex in FSMR
 250  */
 251 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 252 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 253 # define CFG_CPMFCR_RAMTYPE     0
 254 # define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
 255
 256 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 257
 258 /* Define this to reserve an entire FLASH sector (256 KB) for
 259  * environment variables. Otherwise, the environment will be
 260  * put in the same sector as U-Boot, and changing variables
 261  * will erase U-Boot temporarily
 262  */
 263 #define CFG_ENV_IN_OWN_SECT
 264
 265 /* Define to allow the user to overwrite serial and ethaddr */
 266 #define CONFIG_ENV_OVERWRITE
 267
 268 /* What should the console's baud rate be? */
 269 #define CONFIG_BAUDRATE     115200
 270
 271 /* Ethernet MAC address - This is set to all zeros to force an
 272  *                        an error if we use BOOTP without setting
 273  *                        the MAC address
 274  */
 275 #define CONFIG_ETHADDR      00:00:00:00:00:00
 276
 277 /* Set to a positive value to delay for running BOOTCOMMAND */
 278 #define CONFIG_BOOTDELAY    5   /* autoboot after 5 seconds */
 279
 280 /* Be selective on what keys can delay or stop the autoboot process
 281  *     To stop  use: " "
 282  */
 283 #define CONFIG_AUTOBOOT_KEYED
 284 #define CONFIG_AUTOBOOT_PROMPT  "Autobooting in %d seconds, press \" \" to stop\n"
 285 #define CONFIG_AUTOBOOT_STOP_STR    " "
 286 #undef  CONFIG_AUTOBOOT_DELAY_STR
 287 #define DEBUG_BOOTKEYS      0
 288
 289 /* Add support for a few extra bootp options like:
 290  *  - File size
 291  *  - DNS
 292  */
 293 #define CONFIG_BOOTP_MASK   (CONFIG_BOOTP_DEFAULT | \
 294                              CONFIG_BOOTP_BOOTFILESIZE | \
 295                              CONFIG_BOOTP_DNS)
 296
 297 /* undef this to save memory */
 298 #define CFG_LONGHELP
 299
 300 /* Monitor Command Prompt */
 301 #define CFG_PROMPT      "=> "
 302
 303 /* What U-Boot subsytems do you want enabled? */
 304 #define CONFIG_COMMANDS     (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
 305                                CFG_CMD_BEDBUG  | \
 306                                CFG_CMD_ELF | \
 307                                CFG_CMD_ASKENV  | \
 308                                CFG_CMD_ECHO    | \
 309                                CFG_CMD_REGINFO | \
 310                                CFG_CMD_IMMAP   | \
 311                                CFG_CMD_MII)
 312
 313 /* Where do the internal registers live? */
 314 #define CFG_IMMR        0xf0000000
 315
 316 /* Use the HUSH parser */
 317 #define CFG_HUSH_PARSER
 318 #ifdef  CFG_HUSH_PARSER
 319 #define CFG_PROMPT_HUSH_PS2 "> "
 320 #endif
 321
 322 /* What is the address of IO controller */
 323 #define CFG_IO_BASE 0xe0000000
 324
 325 /*****************************************************************************
 326  *
 327  * You should not have to modify any of the following settings
 328  *
 329  *****************************************************************************/
 330
 331 #define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
 332 #define CONFIG_GW8260       1   /* on an GW8260 Board  */
 333
 334 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 335 #include <cmd_confdefs.h>
 336
 337 /*
 338  * Miscellaneous configurable options
 339  */
 340 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 341 #  define CFG_CBSIZE        1024    /* Console I/O Buffer Size       */
 342 #else
 343 #  define CFG_CBSIZE        256     /* Console I/O Buffer Size       */
 344 #endif
 345
 346 /* Print Buffer Size */
 347 #define CFG_PBSIZE    (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
 348
 349 #define CFG_MAXARGS     8          /* max number of command args   */
 350
 351 #define CFG_BARGSIZE    CFG_CBSIZE /* Boot Argument Buffer Size    */
 352
 353 /* Convert clocks to MHZ when passing board info to kernel.
 354  * This must be defined for eariler 2.4 kernels (~2.4.4).
 355  */
 356 #define CONFIG_CLOCKS_IN_MHZ
 357
 358 #define CFG_LOAD_ADDR   0x100000 /* default load address */
 359 #define CFG_HZ          1000     /* decrementer freq: 1 ms ticks */
 360
 361
 362 /* memtest works from the end of the exception vector table
 363  * to the end of the DRAM less monitor and malloc area
 364  */
 365 #define CFG_MEMTEST_START   0x2000
 366
 367 #define CFG_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
 368
 369 #define CFG_MEM_END_USAGE   ( CFG_MONITOR_LEN \
 370                             + CFG_MALLOC_LEN \
 371                             + CFG_ENV_SECT_SIZE \
 372                             + CFG_STACK_USAGE )
 373
 374 #define CFG_MEMTEST_END     ( CFG_SDRAM_SIZE * 1024 * 1024 \
 375                             - CFG_MEM_END_USAGE )
 376
 377 /* valid baudrates */
 378 #define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 379
 380 /*
 381  * Low Level Configuration Settings
 382  * (address mappings, register initial values, etc.)
 383  * You should know what you are doing if you make changes here.
 384  */
 385
 386 #define CFG_FLASH_BASE  CFG_FLASH0_BASE
 387 #define CFG_FLASH_SIZE  CFG_FLASH0_SIZE
 388 #define CFG_SDRAM_BASE  CFG_SDRAM0_BASE
 389 #define CFG_SDRAM_SIZE  CFG_SDRAM0_SIZE
 390
 391 /*-----------------------------------------------------------------------
 392  * Hard Reset Configuration Words
 393  */
 394 #if defined(CFG_SBC_BOOT_LOW)
 395 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 396 #else
 397 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
 398 #endif /* defined(CFG_SBC_BOOT_LOW) */
 399
 400 /* get the HRCW ISB field from CFG_IMMR */
 401 #define CFG_SBC_HRCW_IMMR   ( ((CFG_IMMR & 0x10000000) >> 10) | \
 402                   ((CFG_IMMR & 0x01000000) >>  7) | \
 403                   ((CFG_IMMR & 0x00100000) >>  4) )
 404
 405 #define CFG_HRCW_MASTER     ( HRCW_BPS11                | \
 406                   HRCW_DPPC11               | \
 407                   CFG_SBC_HRCW_IMMR         | \
 408                   HRCW_MMR00                | \
 409                   HRCW_LBPC11               | \
 410                   HRCW_APPC10               | \
 411                   HRCW_CS10PC00             | \
 412                   (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
 413                   CFG_SBC_HRCW_BOOT_FLAGS )
 414
 415 /* no slaves */
 416 #define CFG_HRCW_SLAVE1     0
 417 #define CFG_HRCW_SLAVE2     0
 418 #define CFG_HRCW_SLAVE3     0
 419 #define CFG_HRCW_SLAVE4     0
 420 #define CFG_HRCW_SLAVE5     0
 421 #define CFG_HRCW_SLAVE6     0
 422 #define CFG_HRCW_SLAVE7     0
 423
 424 /*-----------------------------------------------------------------------
 425  * Definitions for initial stack pointer and data area (in DPRAM)
 426  */
 427 #define CFG_INIT_RAM_ADDR    CFG_IMMR
 428 #define CFG_INIT_RAM_END     0x4000  /* End of used area in DPRAM    */
 429 #define CFG_GBL_DATA_SIZE   128 /* bytes reserved for initial data */
 430 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 431 #define CFG_INIT_SP_OFFSET   CFG_GBL_DATA_OFFSET
 432
 433 /*-----------------------------------------------------------------------
 434  * Start addresses for the final memory configuration
 435  * (Set up by the startup code)
 436  * Please note that CFG_SDRAM_BASE _must_ start at 0
 437  * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
 438  */
 439 #define CFG_MONITOR_BASE    CFG_FLASH0_BASE
 440
 441 #define CFG_MONITOR_LEN     (256 * 1024) /* Reserve 256 kB for Monitor   */
 442 #define CFG_MALLOC_LEN      (128 * 1024) /* Reserve 128 kB for malloc()  */
 443
 444 /*
 445  * For booting Linux, the board info and command line data
 446  * have to be in the first 8 MB of memory, since this is
 447  * the maximum mapped by the Linux kernel during initialization.
 448  */
 449 #define CFG_BOOTMAPSZ       (8 * 1024 * 1024) /* Initial Memory map for Linux */
 450
 451 /*-----------------------------------------------------------------------
 452  * FLASH and environment organization
 453  */
 454 #define CFG_MAX_FLASH_BANKS   1    /* max number of memory banks        */
 455 #define CFG_MAX_FLASH_SECT    32   /* max number of sectors on one chip */
 456
 457 #define CFG_FLASH_ERASE_TOUT  8000 /* Timeout for Flash Erase (in ms)   */
 458 #define CFG_FLASH_WRITE_TOUT  1    /* Timeout for Flash Write (in ms)   */
 459
 460 #define CFG_ENV_IS_IN_FLASH   1
 461
 462 #ifdef CFG_ENV_IN_OWN_SECT
 463 #  define CFG_ENV_ADDR        (CFG_MONITOR_BASE +  (256 * 1024))
 464 #  define CFG_ENV_SECT_SIZE   (256 * 1024)
 465 #else
 466 #  define CFG_ENV_SIZE        (16 * 1024)/* Size of Environment Sector  */
 467 #  define CFG_ENV_ADD  ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) - CFG_ENV_SIZE)
 468 #  define CFG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size  */
 469 #endif /* CFG_ENV_IN_OWN_SECT */
 470
 471 /*-----------------------------------------------------------------------
 472  * Cache Configuration
 473  */
 474 #define CFG_CACHELINE_SIZE  32      /* For MPC8260 CPU */
 475
 476 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 477 # define CFG_CACHELINE_SHIFT    5   /* log base 2 of the above value */
 478 #endif
 479
 480 /*-----------------------------------------------------------------------
 481  * HIDx - Hardware Implementation-dependent Registers            2-11
 482  *-----------------------------------------------------------------------
 483  * HID0 also contains cache control - initially enable both caches and
 484  * invalidate contents, then the final state leaves only the instruction
 485  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 486  * but Soft reset does not.
 487  *
 488  * HID1 has only read-only information - nothing to set.
 489  */
 490 #define CFG_HID0_INIT   (HID0_ICE  |\
 491                          HID0_DCE  |\
 492                          HID0_ICFI |\
 493                          HID0_DCI  |\
 494                          HID0_IFEM |\
 495                          HID0_ABE)
 496
 497 #define CFG_HID0_FINAL  (HID0_ICE  |\
 498                          HID0_IFEM |\
 499                          HID0_ABE  |\
 500                          HID0_EMCP)
 501 #define CFG_HID2    0
 502
 503 /*-----------------------------------------------------------------------
 504  * RMR - Reset Mode Register
 505  *-----------------------------------------------------------------------
 506  */
 507 #define CFG_RMR     0
 508
 509 /*-----------------------------------------------------------------------
 510  * BCR - Bus Configuration                           4-25
 511  *-----------------------------------------------------------------------
 512  */
 513 #define CFG_BCR     (BCR_ETM)
 514
 515 /*-----------------------------------------------------------------------
 516  * SIUMCR - SIU Module Configuration                 4-31
 517  *-----------------------------------------------------------------------
 518  */
 519 #define CFG_SIUMCR  (SIUMCR_DPPC11  |\
 520                      SIUMCR_L2CPC00 |\
 521                      SIUMCR_APPC10  |\
 522                      SIUMCR_MMR00)
 523
 524
 525 /*-----------------------------------------------------------------------
 526  * SYPCR - System Protection Control                11-9
 527  * SYPCR can only be written once after reset!
 528  *-----------------------------------------------------------------------
 529  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 530  */
 531 #define CFG_SYPCR   (SYPCR_SWTC |\
 532                      SYPCR_BMT  |\
 533                      SYPCR_PBME |\
 534                      SYPCR_LBME |\
 535                      SYPCR_SWRI |\
 536                      SYPCR_SWP)
 537
 538 /*-----------------------------------------------------------------------
 539  * TMCNTSC - Time Counter Status and Control             4-40
 540  *-----------------------------------------------------------------------
 541  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 542  * and enable Time Counter
 543  */
 544 #define CFG_TMCNTSC (TMCNTSC_SEC |\
 545                      TMCNTSC_ALR |\
 546                      TMCNTSC_TCF |\
 547                      TMCNTSC_TCE)
 548
 549 /*-----------------------------------------------------------------------
 550  * PISCR - Periodic Interrupt Status and Control         4-42
 551  *-----------------------------------------------------------------------
 552  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 553  * Periodic timer
 554  */
 555 #define CFG_PISCR   (PISCR_PS  |\
 556                      PISCR_PTF |\
 557                      PISCR_PTE)
 558
 559 /*-----------------------------------------------------------------------
 560  * SCCR - System Clock Control                           9-8
 561  *-----------------------------------------------------------------------
 562  */
 563 #define CFG_SCCR    0
 564
 565 /*-----------------------------------------------------------------------
 566  * RCCR - RISC Controller Configuration                 13-7
 567  *-----------------------------------------------------------------------
 568  */
 569 #define CFG_RCCR    0
 570
 571 /*
 572  * Initialize Memory Controller:
 573  *
 574  * Bank Bus   Machine PortSz  Device
 575  * ---- ---   ------- ------  ------
 576  *  0   60x   GPCM    32 bit  FLASH (SIMM - 4MB)
 577  *  1   60x   GPCM    32 bit  unused
 578  *  2   60x   SDRAM   64 bit  SDRAM (DIMM - 16MB or 64MB)
 579  *  3   60x   SDRAM   64 bit  unused
 580  *  4   Local GPCM     8 bit  IO    (on board - 64k)
 581  *  5   60x   GPCM     8 bit  unused
 582  *  6   60x   GPCM     8 bit  unused
 583  *  7   60x   GPCM     8 bit  unused
 584  *
 585  */
 586
 587 /*-----------------------------------------------------------------------
 588  * BR0 - Base Register
 589  *     Ref: Section 10.3.1 on page 10-14
 590  * OR0 - Option Register
 591  *     Ref: Section 10.3.2 on page 10-18
 592  *-----------------------------------------------------------------------
 593  */
 594
 595 /* Bank 0,1 - FLASH SIMM
 596  *
 597  * This expects the FLASH SIMM to be connected to *CS0
 598  * It consists of 4 AM29F016D parts.
 599  *
 600  * Note: For the 8 MB SIMM, *CS1 is unused.
 601  */
 602
 603 /* BR0 is configured as follows:
 604  *
 605  *     - Base address of 0x40000000
 606  *     - 32 bit port size
 607  *     - Data errors checking is disabled
 608  *     - Read and write access
 609  *     - GPCM 60x bus
 610  *     - Access are handled by the memory controller according to MSEL
 611  *     - Not used for atomic operations
 612  *     - No data pipelining is done
 613  *     - Valid
 614  */
 615 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
 616                           BRx_PS_32                     |\
 617                           BRx_MS_GPCM_P                 |\
 618                           BRx_V)
 619
 620 /* OR0 is configured as follows:
 621  *
 622  *     - 8 MB
 623  *     - *BCTL0 is asserted upon access to the current memory bank
 624  *     - *CW / *WE are negated a quarter of a clock earlier
 625  *     - *CS is output at the same time as the address lines
 626  *     - Uses a clock cycle length of 5
 627  *     - *PSDVAL is generated internally by the memory controller
 628  *       unless *GTA is asserted earlier externally.
 629  *     - Relaxed timing is generated by the GPCM for accesses
 630  *       initiated to this memory region.
 631  *     - One idle clock is inserted between a read access from the
 632  *       current bank and the next access.
 633  */
 634 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE) |\
 635                          ORxG_CSNT          |\
 636                          ORxG_ACS_DIV1      |\
 637                          ORxG_SCY_5_CLK     |\
 638                          ORxG_TRLX          |\
 639                          ORxG_EHTR)
 640
 641 /*-----------------------------------------------------------------------
 642  * BR2 - Base Register
 643  *     Ref: Section 10.3.1 on page 10-14
 644  * OR2 - Option Register
 645  *     Ref: Section 10.3.2 on page 10-16
 646  *-----------------------------------------------------------------------
 647  */
 648
 649 /* Bank 2 - SDRAM DIMM
 650  *
 651  *     16MB DIMM: P/N
 652  *     64MB DIMM: P/N  1W-8864X8-4-P1-EST or
 653  *                     MT4LSDT864AG-10EB1 (Micron)
 654  *
 655  * Note: *CS3 is unused for this DIMM
 656  */
 657
 658 /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
 659  *
 660  *     - Base address of 0x00000000
 661  *     - 64 bit port size (60x bus only)
 662  *     - Data errors checking is disabled
 663  *     - Read and write access
 664  *     - SDRAM 60x bus
 665  *     - Access are handled by the memory controller according to MSEL
 666  *     - Not used for atomic operations
 667  *     - No data pipelining is done
 668  *     - Valid
 669  */
 670 #define CFG_BR2_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 671                           BRx_PS_64          |\
 672                           BRx_MS_SDRAM_P     |\
 673                           BRx_V)
 674
 675 /* With a 16 MB DIMM, the OR2 is configured as follows:
 676  *
 677  *     - 16 MB
 678  *     - 2 internal banks per device
 679  *     - Row start address bit is A9 with PSDMR[PBI] = 0
 680  *     - 11 row address lines
 681  *     - Back-to-back page mode
 682  *     - Internal bank interleaving within save device enabled
 683  */
 684 #if (CFG_SDRAM0_SIZE == 16)
 685 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
 686                          ORxS_BPD_2         |\
 687                          ORxS_ROWST_PBI0_A9 |\
 688                          ORxS_NUMR_11)
 689
 690 /* With a 16 MB DIMM, the PSDMR is configured as follows:
 691  *
 692  *     - Page Based Interleaving,
 693  *     - Refresh Enable,
 694  *     - Address Multiplexing where A5 is output on A14 pin
 695  *       (A6 on A15, and so on),
 696  *     - use address pins A16-A18 as bank select,
 697  *     - A9 is output on SDA10 during an ACTIVATE command,
 698  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 699  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 700  *       is 3 clocks,
 701  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 702  *       2 clocks,
 703  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 704  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 705  *     - CAS Latency is 2.
 706  */
 707
 708 /*-----------------------------------------------------------------------
 709  * PSDMR - 60x Bus SDRAM Mode Register
 710  *     Ref: Section 10.3.3 on page 10-21
 711  *-----------------------------------------------------------------------
 712  */
 713 #define CFG_PSDMR   (PSDMR_RFEN       |\
 714                      PSDMR_SDAM_A14_IS_A5 |\
 715                      PSDMR_BSMA_A16_A18   |\
 716                      PSDMR_SDA10_PBI0_A9  |\
 717                      PSDMR_RFRC_7_CLK     |\
 718                      PSDMR_PRETOACT_3W    |\
 719                      PSDMR_ACTTORW_2W     |\
 720                      PSDMR_LDOTOPRE_1C    |\
 721                      PSDMR_WRC_1C         |\
 722                      PSDMR_CL_2)
 723 #endif /* (CFG_SDRAM0_SIZE == 16) */
 724
 725 /* With a 64 MB DIMM, the OR2 is configured as follows:
 726  *
 727  *     - 64 MB
 728  *     - 4 internal banks per device
 729  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 730  *     - 12 row address lines
 731  *     - Back-to-back page mode
 732  *     - Internal bank interleaving within save device enabled
 733  */
 734 #if (CFG_SDRAM0_SIZE == 64)
 735 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
 736              ORxS_BPD_4         |\
 737              ORxS_ROWST_PBI0_A8     |\
 738              ORxS_NUMR_12)
 739
 740 /* With a 64 MB DIMM, the PSDMR is configured as follows:
 741  *
 742  *     - Page Based Interleaving,
 743  *     - Refresh Enable,
 744  *     - Address Multiplexing where A5 is output on A14 pin
 745  *       (A6 on A15, and so on),
 746  *     - use address pins A14-A16 as bank select,
 747  *     - A9 is output on SDA10 during an ACTIVATE command,
 748  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 749  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 750  *       is 3 clocks,
 751  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 752  *       2 clocks,
 753  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 754  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 755  *     - CAS Latency is 2.
 756  */
 757
 758 /*-----------------------------------------------------------------------
 759  * PSDMR - 60x Bus SDRAM Mode Register
 760  *     Ref: Section 10.3.3 on page 10-21
 761  *-----------------------------------------------------------------------
 762  */
 763 #define CFG_PSDMR   (PSDMR_RFEN       |\
 764                      PSDMR_SDAM_A14_IS_A5 |\
 765                      PSDMR_BSMA_A14_A16   |\
 766                      PSDMR_SDA10_PBI0_A9  |\
 767                      PSDMR_RFRC_7_CLK     |\
 768                      PSDMR_PRETOACT_3W    |\
 769                      PSDMR_ACTTORW_2W     |\
 770                      PSDMR_LDOTOPRE_1C    |\
 771                      PSDMR_WRC_1C         |\
 772                      PSDMR_CL_2)
 773 #endif  /* (CFG_SDRAM0_SIZE == 64) */
 774
 775 #define CFG_PSRT    0x0e
 776 #define CFG_MPTPR   MPTPR_PTP_DIV32
 777
 778
 779 /*-----------------------------------------------------------------------
 780  * BR4 - Base Register
 781  *     Ref: Section 10.3.1 on page 10-14
 782  * OR4 - Option Register
 783  *     Ref: Section 10.3.2 on page 10-18
 784  *-----------------------------------------------------------------------
 785  */
 786 /* Bank 4 - Onboard Memory Mapped IO controller
 787  *
 788  * This expects the onboard IO controller to connected to *CS4 and
 789  * the local bus.
 790  *     - Base address of 0xe0000000
 791  *     - 8 bit port size (local bus only)
 792  *     - Read and write access
 793  *     - GPCM local bus
 794  *     - Not used for atomic operations
 795  *     - No data pipelining is done
 796  *     - Valid
 797  *     - extended hold time
 798  *     - 11 wait states
 799  */
 800
 801 #ifdef CFG_IO_BASE
 802 #  define CFG_BR4_PRELIM  ((CFG_IO_BASE & BRx_BA_MSK)  |\
 803                             BRx_PS_8                   |\
 804                             BRx_MS_GPCM_L              |\
 805                             BRx_V)
 806
 807 #  define CFG_OR4_PRELIM   (ORxG_AM_MSK                |\
 808                             ORxG_SCY_11_CLK            |\
 809                             ORxG_EHTR)
 810 #endif /* CFG_IO_BASE */
 811
 812 /*
 813  * Internal Definitions
 814  *
 815  * Boot Flags
 816  */
 817 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 818 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 819
 820 #endif  /* __CONFIG_H */