include/configs/gw8260.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2001
  10  * Advent Networks, Inc. <http://www.adventnetworks.com>
  11  * Jay Monkman <jmonkman@adventnetworks.com>
  12  *
  13  * (C) Copyright 2001
  14  * Advent Networks, Inc. <http://www.adventnetworks.com>
  15  * Oliver Brown <obrown@adventnetworks.com>
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35
  36 /*********************************************************************/
  37 /* DESCRIPTION:
  38  *   This file contains the board configuartion for the GW8260 board.
  39  *
  40  * MODULE DEPENDENCY:
  41  *   None
  42  *
  43  * RESTRICTIONS/LIMITATIONS:
  44  *   None
  45  *
  46  * Copyright (c) 2001, Advent Networks, Inc.
  47  */
  48 /*********************************************************************/
  49
  50 #ifndef __CONFIG_H
  51 #define __CONFIG_H
  52
  53 /* Enable debug prints */
  54 #undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
  55
  56 /* What is the oscillator's (UX2) frequency in Hz? */
  57 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  58
  59 /*-----------------------------------------------------------------------
  60  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  61  *-----------------------------------------------------------------------
  62  * What should MODCK_H be? It is dependent on the oscillator
  63  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  64  * Here are some example values (all frequencies are in MHz):
  65  *
  66  * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
  67  * -------   ----------  ---    ---    ----  -----  -----  -----
  68  * 0x5       0x5     66 133     133    Open  Close  Open
  69  * 0x5       0x6     66 133     166    Open  Open   Close
  70  * 0x5       0x7     66 133     200    Open  Open   Open
  71  * 0x6       0x0     66 133     233    Close Close  Close
  72  * 0x6       0x1     66 133     266    Close Close  Open
  73  * 0x6       0x2     66 133     300    Close Open   Close
  74  */
  75 #define CONFIG_SYS_SBC_MODCK_H 0x05
  76
  77 /* Define this if you want to boot from 0x00000100. If you don't define
  78  * this, you will need to program the bootloader to 0xfff00000, and
  79  * get the hardware reset config words at 0xfe000000. The simplest
  80  * way to do that is to program the bootloader at both addresses.
  81  * It is suggested that you just let U-Boot live at 0x00000000.
  82  */
  83 #define CONFIG_SYS_SBC_BOOT_LOW 1
  84
  85 /* What should the base address of the main FLASH be and how big is
  86  * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
  87  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  88  * this to be the SIMM.
  89  */
  90 #define CONFIG_SYS_FLASH0_BASE 0x40000000
  91 #define CONFIG_SYS_FLASH0_SIZE 8
  92
  93 /* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
  94  * Note: the 'flashchecksum' environment variable must also be set to 'y'.
  95  */
  96 #define CONFIG_SYS_FLASH_CHECKSUM
  97
  98 /* What should be the base address of SDRAM DIMM and how big is
  99  * it (in Mbytes)?
 100  */
 101 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
 102 #define CONFIG_SYS_SDRAM0_SIZE 64
 103
 104 /*
 105  * DRAM tests
 106  *   CONFIG_SYS_DRAM_TEST - enables the following tests.
 107  *
 108  *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
 109  *                        Environment variable 'test_dram_data' must be
 110  *                        set to 'y'.
 111  *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
 112  *                        addressable. Environment variable
 113  *                        'test_dram_address' must be set to 'y'.
 114  *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
 115  *                        This test takes about 6 minutes to test 64 MB.
 116  *                        Environment variable 'test_dram_walk' must be
 117  *                        set to 'y'.
 118  */
 119 #define CONFIG_SYS_DRAM_TEST
 120 #if defined(CONFIG_SYS_DRAM_TEST)
 121 #define CONFIG_SYS_DRAM_TEST_DATA
 122 #define CONFIG_SYS_DRAM_TEST_ADDRESS
 123 #define CONFIG_SYS_DRAM_TEST_WALK
 124 #endif /* CONFIG_SYS_DRAM_TEST */
 125
 126 /*
 127  * GW8260 with 16 MB DIMM:
 128  *
 129  *     0x0000 0000     Exception Vector code, 8k
 130  *           :
 131  *     0x0000 1FFF
 132  *     0x0000 2000     Free for Application Use
 133  *           :
 134  *           :
 135  *
 136  *           :
 137  *           :
 138  *     0x00F5 FF30     Monitor Stack (Growing downward)
 139  *                     Monitor Stack Buffer (0x80)
 140  *     0x00F5 FFB0     Board Info Data
 141  *     0x00F6 0000     Malloc Arena
 142  *           :          CONFIG_ENV_SECT_SIZE, 256k
 143  *           :          CONFIG_SYS_MALLOC_LEN,    128k
 144  *     0x00FC 0000     RAM Copy of Monitor Code
 145  *           :              CONFIG_SYS_MONITOR_LEN,   256k
 146  *     0x00FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
 147  */
 148
 149 /*
 150  * GW8260 with 64 MB DIMM:
 151  *
 152  *     0x0000 0000     Exception Vector code, 8k
 153  *           :
 154  *     0x0000 1FFF
 155  *     0x0000 2000     Free for Application Use
 156  *           :
 157  *           :
 158  *
 159  *           :
 160  *           :
 161  *     0x03F5 FF30     Monitor Stack (Growing downward)
 162  *                     Monitor Stack Buffer (0x80)
 163  *     0x03F5 FFB0     Board Info Data
 164  *     0x03F6 0000     Malloc Arena
 165  *           :          CONFIG_ENV_SECT_SIZE, 256k
 166  *           :          CONFIG_SYS_MALLOC_LEN,    128k
 167  *     0x03FC 0000     RAM Copy of Monitor Code
 168  *           :              CONFIG_SYS_MONITOR_LEN,   256k
 169  *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
 170  */
 171
 172
 173 /*
 174  * select serial console configuration
 175  *
 176  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 177  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 178  * for SCC).
 179  *
 180  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 181  * defined elsewhere.
 182  */
 183 #define CONFIG_CONS_ON_SMC  1   /* define if console on SMC */
 184 #undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
 185 #undef  CONFIG_CONS_NONE        /* define if console on neither */
 186 #define CONFIG_CONS_INDEX   1   /* which SMC/SCC channel for console */
 187
 188 /*
 189  * select ethernet configuration
 190  *
 191  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 192  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 193  * for FCC)
 194  *
 195  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 196  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 197  */
 198
 199 #undef  CONFIG_ETHER_ON_SCC
 200 #define CONFIG_ETHER_ON_FCC
 201 #undef  CONFIG_ETHER_NONE       /* define if ethernet on neither */
 202
 203 #ifdef  CONFIG_ETHER_ON_SCC
 204 #define CONFIG_ETHER_INDEX  1   /* which SCC/FCC channel for ethernet */
 205 #endif  /* CONFIG_ETHER_ON_SCC */
 206
 207 #ifdef  CONFIG_ETHER_ON_FCC
 208 #define CONFIG_ETHER_INDEX  2   /* which SCC/FCC channel for ethernet */
 209 #define CONFIG_MII              /* MII PHY management           */
 210 #define CONFIG_BITBANGMII       /* bit-bang MII PHY management  */
 211 /*
 212  * Port pins used for bit-banged MII communictions (if applicable).
 213  */
 214 #define MDIO_PORT   2       /* Port C */
 215 #define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
 216 #define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
 217 #define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
 218
 219 #define MDIO(bit)   if(bit) iop->pdat |=  0x00400000; \
 220             else            iop->pdat &= ~0x00400000
 221
 222 #define MDC(bit)    if(bit) iop->pdat |=  0x00200000; \
 223             else    iop->pdat &= ~0x00200000
 224
 225 #define MIIDELAY    udelay(1)
 226 #endif  /* CONFIG_ETHER_ON_FCC */
 227
 228 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 229
 230 /*
 231  * - Rx-CLK is CLK13
 232  * - Tx-CLK is CLK14
 233  * - Select bus for bd/buffers (see 28-13)
 234  * - Enable Full Duplex in FSMR
 235  */
 236 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 237 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 238 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 239 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 240
 241 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 242
 243 /*
 244  * - Rx-CLK is CLK15
 245  * - Tx-CLK is CLK16
 246  * - Select bus for bd/buffers (see 28-13)
 247  * - Enable Full Duplex in FSMR
 248  */
 249 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 250 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 251 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 252 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 253
 254 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 255
 256 /* Define this to reserve an entire FLASH sector (256 KB) for
 257  * environment variables. Otherwise, the environment will be
 258  * put in the same sector as U-Boot, and changing variables
 259  * will erase U-Boot temporarily
 260  */
 261 #define CONFIG_ENV_IN_OWN_SECT
 262
 263 /* Define to allow the user to overwrite serial and ethaddr */
 264 #define CONFIG_ENV_OVERWRITE
 265
 266 /* What should the console's baud rate be? */
 267 #define CONFIG_BAUDRATE     115200
 268
 269 /* Ethernet MAC address - This is set to all zeros to force an
 270  *                        an error if we use BOOTP without setting
 271  *                        the MAC address
 272  */
 273 #define CONFIG_ETHADDR      00:00:00:00:00:00
 274
 275 /* Set to a positive value to delay for running BOOTCOMMAND */
 276 #define CONFIG_BOOTDELAY    5   /* autoboot after 5 seconds */
 277
 278 /* Be selective on what keys can delay or stop the autoboot process
 279  *     To stop  use: " "
 280  */
 281 #define CONFIG_AUTOBOOT_KEYED
 282 #define CONFIG_AUTOBOOT_PROMPT  \
 283         "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
 284 #define CONFIG_AUTOBOOT_STOP_STR    " "
 285 #undef  CONFIG_AUTOBOOT_DELAY_STR
 286 #define DEBUG_BOOTKEYS      0
 287
 288 /*
 289  * BOOTP options
 290  */
 291 #define CONFIG_BOOTP_SUBNETMASK
 292 #define CONFIG_BOOTP_GATEWAY
 293 #define CONFIG_BOOTP_HOSTNAME
 294 #define CONFIG_BOOTP_BOOTPATH
 295
 296 #define CONFIG_BOOTP_BOOTFILESIZE
 297 #define CONFIG_BOOTP_DNS
 298
 299 /* undef this to save memory */
 300 #define CONFIG_SYS_LONGHELP
 301
 302 /* Monitor Command Prompt */
 303 #define CONFIG_SYS_PROMPT      "=> "
 304
 305
 306 /*
 307  * Command line configuration.
 308  */
 309 #include <config_cmd_default.h>
 310
 311 #define CONFIG_CMD_BEDBUG
 312 #define CONFIG_CMD_ELF
 313 #define CONFIG_CMD_ASKENV
 314 #define CONFIG_CMD_REGINFO
 315 #define CONFIG_CMD_IMMAP
 316 #define CONFIG_CMD_MII
 317
 318 #undef CONFIG_CMD_KGDB
 319
 320
 321 /* Where do the internal registers live? */
 322 #define CONFIG_SYS_IMMR        0xf0000000
 323
 324 /* Use the HUSH parser */
 325 #define CONFIG_SYS_HUSH_PARSER
 326 #ifdef  CONFIG_SYS_HUSH_PARSER
 327 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 328 #endif
 329
 330 /* What is the address of IO controller */
 331 #define CONFIG_SYS_IO_BASE 0xe0000000
 332
 333 /*****************************************************************************
 334  *
 335  * You should not have to modify any of the following settings
 336  *
 337  *****************************************************************************/
 338
 339 #define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
 340 #define CONFIG_GW8260       1   /* on an GW8260 Board  */
 341 #define CONFIG_CPM2             1       /* Has a CPM2 */
 342
 343 /*
 344  * Miscellaneous configurable options
 345  */
 346 #if defined(CONFIG_CMD_KGDB)
 347 #  define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size       */
 348 #else
 349 #  define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size       */
 350 #endif
 351
 352 /* Print Buffer Size */
 353 #define CONFIG_SYS_PBSIZE    (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 354
 355 #define CONFIG_SYS_MAXARGS     8          /* max number of command args   */
 356
 357 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size    */
 358
 359 /* Convert clocks to MHZ when passing board info to kernel.
 360  * This must be defined for eariler 2.4 kernels (~2.4.4).
 361  */
 362 #define CONFIG_CLOCKS_IN_MHZ
 363
 364 #define CONFIG_SYS_LOAD_ADDR   0x100000 /* default load address */
 365 #define CONFIG_SYS_HZ          1000     /* decrementer freq: 1 ms ticks */
 366
 367
 368 /* memtest works from the end of the exception vector table
 369  * to the end of the DRAM less monitor and malloc area
 370  */
 371 #define CONFIG_SYS_MEMTEST_START   0x2000
 372
 373 #define CONFIG_SYS_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
 374
 375 #define CONFIG_SYS_MEM_END_USAGE   ( CONFIG_SYS_MONITOR_LEN \
 376                             + CONFIG_SYS_MALLOC_LEN \
 377                             + CONFIG_ENV_SECT_SIZE \
 378                             + CONFIG_SYS_STACK_USAGE )
 379
 380 #define CONFIG_SYS_MEMTEST_END     ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
 381                             - CONFIG_SYS_MEM_END_USAGE )
 382
 383 /* valid baudrates */
 384 #define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
 385
 386 /*
 387  * Low Level Configuration Settings
 388  * (address mappings, register initial values, etc.)
 389  * You should know what you are doing if you make changes here.
 390  */
 391
 392 #define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_FLASH0_BASE
 393 #define CONFIG_SYS_FLASH_SIZE  CONFIG_SYS_FLASH0_SIZE
 394 #define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_SDRAM0_BASE
 395 #define CONFIG_SYS_SDRAM_SIZE  CONFIG_SYS_SDRAM0_SIZE
 396
 397 /*-----------------------------------------------------------------------
 398  * Hard Reset Configuration Words
 399  */
 400 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
 401 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 402 #else
 403 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
 404 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 405
 406 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
 407 #define CONFIG_SYS_SBC_HRCW_IMMR   ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
 408                   ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
 409                   ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
 410
 411 #define CONFIG_SYS_HRCW_MASTER     ( HRCW_BPS11                | \
 412                   HRCW_DPPC11               | \
 413                   CONFIG_SYS_SBC_HRCW_IMMR         | \
 414                   HRCW_MMR00                | \
 415                   HRCW_LBPC11               | \
 416                   HRCW_APPC10               | \
 417                   HRCW_CS10PC00             | \
 418                   (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
 419                   CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
 420
 421 /* no slaves */
 422 #define CONFIG_SYS_HRCW_SLAVE1     0
 423 #define CONFIG_SYS_HRCW_SLAVE2     0
 424 #define CONFIG_SYS_HRCW_SLAVE3     0
 425 #define CONFIG_SYS_HRCW_SLAVE4     0
 426 #define CONFIG_SYS_HRCW_SLAVE5     0
 427 #define CONFIG_SYS_HRCW_SLAVE6     0
 428 #define CONFIG_SYS_HRCW_SLAVE7     0
 429
 430 /*-----------------------------------------------------------------------
 431  * Definitions for initial stack pointer and data area (in DPRAM)
 432  */
 433 #define CONFIG_SYS_INIT_RAM_ADDR    CONFIG_SYS_IMMR
 434 #define CONFIG_SYS_INIT_RAM_END     0x4000  /* End of used area in DPRAM    */
 435 #define CONFIG_SYS_GBL_DATA_SIZE   128 /* bytes reserved for initial data */
 436 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 437 #define CONFIG_SYS_INIT_SP_OFFSET   CONFIG_SYS_GBL_DATA_OFFSET
 438
 439 /*-----------------------------------------------------------------------
 440  * Start addresses for the final memory configuration
 441  * (Set up by the startup code)
 442  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 443  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 444  */
 445 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH0_BASE
 446
 447 #define CONFIG_SYS_MONITOR_LEN     (256 * 1024) /* Reserve 256 kB for Monitor   */
 448 #define CONFIG_SYS_MALLOC_LEN      (128 * 1024) /* Reserve 128 kB for malloc()  */
 449
 450 /*
 451  * For booting Linux, the board info and command line data
 452  * have to be in the first 8 MB of memory, since this is
 453  * the maximum mapped by the Linux kernel during initialization.
 454  */
 455 #define CONFIG_SYS_BOOTMAPSZ       (8 * 1024 * 1024) /* Initial Memory map for Linux */
 456
 457 /*-----------------------------------------------------------------------
 458  * FLASH and environment organization
 459  */
 460 #define CONFIG_SYS_MAX_FLASH_BANKS   1    /* max number of memory banks        */
 461 #define CONFIG_SYS_MAX_FLASH_SECT    32   /* max number of sectors on one chip */
 462
 463 #define CONFIG_SYS_FLASH_ERASE_TOUT  8000 /* Timeout for Flash Erase (in ms)   */
 464 #define CONFIG_SYS_FLASH_WRITE_TOUT  1    /* Timeout for Flash Write (in ms)   */
 465
 466 #define CONFIG_ENV_IS_IN_FLASH   1
 467
 468 #ifdef CONFIG_ENV_IN_OWN_SECT
 469 #  define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE +  (256 * 1024))
 470 #  define CONFIG_ENV_SECT_SIZE   (256 * 1024)
 471 #else
 472 #  define CONFIG_ENV_SIZE        (16 * 1024)/* Size of Environment Sector  */
 473 #  define CONFIG_ENV_ADD  ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
 474 #  define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size  */
 475 #endif /* CONFIG_ENV_IN_OWN_SECT */
 476
 477 /*-----------------------------------------------------------------------
 478  * Cache Configuration
 479  */
 480 #define CONFIG_SYS_CACHELINE_SIZE  32      /* For MPC8260 CPU */
 481
 482 #if defined(CONFIG_CMD_KGDB)
 483 # define CONFIG_SYS_CACHELINE_SHIFT    5   /* log base 2 of the above value */
 484 #endif
 485
 486 /*-----------------------------------------------------------------------
 487  * HIDx - Hardware Implementation-dependent Registers            2-11
 488  *-----------------------------------------------------------------------
 489  * HID0 also contains cache control - initially enable both caches and
 490  * invalidate contents, then the final state leaves only the instruction
 491  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 492  * but Soft reset does not.
 493  *
 494  * HID1 has only read-only information - nothing to set.
 495  */
 496 #define CONFIG_SYS_HID0_INIT   (HID0_ICE  |\
 497                          HID0_DCE  |\
 498                          HID0_ICFI |\
 499                          HID0_DCI  |\
 500                          HID0_IFEM |\
 501                          HID0_ABE)
 502
 503 #define CONFIG_SYS_HID0_FINAL  (HID0_ICE  |\
 504                          HID0_IFEM |\
 505                          HID0_ABE  |\
 506                          HID0_EMCP)
 507 #define CONFIG_SYS_HID2    0
 508
 509 /*-----------------------------------------------------------------------
 510  * RMR - Reset Mode Register
 511  *-----------------------------------------------------------------------
 512  */
 513 #define CONFIG_SYS_RMR     0
 514
 515 /*-----------------------------------------------------------------------
 516  * BCR - Bus Configuration                           4-25
 517  *-----------------------------------------------------------------------
 518  */
 519 #define CONFIG_SYS_BCR     (BCR_ETM)
 520
 521 /*-----------------------------------------------------------------------
 522  * SIUMCR - SIU Module Configuration                 4-31
 523  *-----------------------------------------------------------------------
 524  */
 525 #define CONFIG_SYS_SIUMCR  (SIUMCR_DPPC11  |\
 526                      SIUMCR_L2CPC00 |\
 527                      SIUMCR_APPC10  |\
 528                      SIUMCR_MMR00)
 529
 530
 531 /*-----------------------------------------------------------------------
 532  * SYPCR - System Protection Control                11-9
 533  * SYPCR can only be written once after reset!
 534  *-----------------------------------------------------------------------
 535  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 536  */
 537 #define CONFIG_SYS_SYPCR   (SYPCR_SWTC |\
 538                      SYPCR_BMT  |\
 539                      SYPCR_PBME |\
 540                      SYPCR_LBME |\
 541                      SYPCR_SWRI |\
 542                      SYPCR_SWP)
 543
 544 /*-----------------------------------------------------------------------
 545  * TMCNTSC - Time Counter Status and Control             4-40
 546  *-----------------------------------------------------------------------
 547  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 548  * and enable Time Counter
 549  */
 550 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
 551                      TMCNTSC_ALR |\
 552                      TMCNTSC_TCF |\
 553                      TMCNTSC_TCE)
 554
 555 /*-----------------------------------------------------------------------
 556  * PISCR - Periodic Interrupt Status and Control         4-42
 557  *-----------------------------------------------------------------------
 558  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 559  * Periodic timer
 560  */
 561 #define CONFIG_SYS_PISCR   (PISCR_PS  |\
 562                      PISCR_PTF |\
 563                      PISCR_PTE)
 564
 565 /*-----------------------------------------------------------------------
 566  * SCCR - System Clock Control                           9-8
 567  *-----------------------------------------------------------------------
 568  */
 569 #define CONFIG_SYS_SCCR    0
 570
 571 /*-----------------------------------------------------------------------
 572  * RCCR - RISC Controller Configuration                 13-7
 573  *-----------------------------------------------------------------------
 574  */
 575 #define CONFIG_SYS_RCCR    0
 576
 577 /*
 578  * Initialize Memory Controller:
 579  *
 580  * Bank Bus   Machine PortSz  Device
 581  * ---- ---   ------- ------  ------
 582  *  0   60x   GPCM    32 bit  FLASH (SIMM - 4MB)
 583  *  1   60x   GPCM    32 bit  unused
 584  *  2   60x   SDRAM   64 bit  SDRAM (DIMM - 16MB or 64MB)
 585  *  3   60x   SDRAM   64 bit  unused
 586  *  4   Local GPCM     8 bit  IO    (on board - 64k)
 587  *  5   60x   GPCM     8 bit  unused
 588  *  6   60x   GPCM     8 bit  unused
 589  *  7   60x   GPCM     8 bit  unused
 590  *
 591  */
 592
 593 /*-----------------------------------------------------------------------
 594  * BR0 - Base Register
 595  *     Ref: Section 10.3.1 on page 10-14
 596  * OR0 - Option Register
 597  *     Ref: Section 10.3.2 on page 10-18
 598  *-----------------------------------------------------------------------
 599  */
 600
 601 /* Bank 0,1 - FLASH SIMM
 602  *
 603  * This expects the FLASH SIMM to be connected to *CS0
 604  * It consists of 4 AM29F016D parts.
 605  *
 606  * Note: For the 8 MB SIMM, *CS1 is unused.
 607  */
 608
 609 /* BR0 is configured as follows:
 610  *
 611  *     - Base address of 0x40000000
 612  *     - 32 bit port size
 613  *     - Data errors checking is disabled
 614  *     - Read and write access
 615  *     - GPCM 60x bus
 616  *     - Access are handled by the memory controller according to MSEL
 617  *     - Not used for atomic operations
 618  *     - No data pipelining is done
 619  *     - Valid
 620  */
 621 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 622                           BRx_PS_32                     |\
 623                           BRx_MS_GPCM_P                 |\
 624                           BRx_V)
 625
 626 /* OR0 is configured as follows:
 627  *
 628  *     - 8 MB
 629  *     - *BCTL0 is asserted upon access to the current memory bank
 630  *     - *CW / *WE are negated a quarter of a clock earlier
 631  *     - *CS is output at the same time as the address lines
 632  *     - Uses a clock cycle length of 5
 633  *     - *PSDVAL is generated internally by the memory controller
 634  *       unless *GTA is asserted earlier externally.
 635  *     - Relaxed timing is generated by the GPCM for accesses
 636  *       initiated to this memory region.
 637  *     - One idle clock is inserted between a read access from the
 638  *       current bank and the next access.
 639  */
 640 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
 641                          ORxG_CSNT          |\
 642                          ORxG_ACS_DIV1      |\
 643                          ORxG_SCY_5_CLK     |\
 644                          ORxG_TRLX          |\
 645                          ORxG_EHTR)
 646
 647 /*-----------------------------------------------------------------------
 648  * BR2 - Base Register
 649  *     Ref: Section 10.3.1 on page 10-14
 650  * OR2 - Option Register
 651  *     Ref: Section 10.3.2 on page 10-16
 652  *-----------------------------------------------------------------------
 653  */
 654
 655 /* Bank 2 - SDRAM DIMM
 656  *
 657  *     16MB DIMM: P/N
 658  *     64MB DIMM: P/N  1W-8864X8-4-P1-EST or
 659  *                     MT4LSDT864AG-10EB1 (Micron)
 660  *
 661  * Note: *CS3 is unused for this DIMM
 662  */
 663
 664 /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
 665  *
 666  *     - Base address of 0x00000000
 667  *     - 64 bit port size (60x bus only)
 668  *     - Data errors checking is disabled
 669  *     - Read and write access
 670  *     - SDRAM 60x bus
 671  *     - Access are handled by the memory controller according to MSEL
 672  *     - Not used for atomic operations
 673  *     - No data pipelining is done
 674  *     - Valid
 675  */
 676 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 677                           BRx_PS_64          |\
 678                           BRx_MS_SDRAM_P     |\
 679                           BRx_V)
 680
 681 /* With a 16 MB DIMM, the OR2 is configured as follows:
 682  *
 683  *     - 16 MB
 684  *     - 2 internal banks per device
 685  *     - Row start address bit is A9 with PSDMR[PBI] = 0
 686  *     - 11 row address lines
 687  *     - Back-to-back page mode
 688  *     - Internal bank interleaving within save device enabled
 689  */
 690 #if (CONFIG_SYS_SDRAM0_SIZE == 16)
 691 #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
 692                          ORxS_BPD_2         |\
 693                          ORxS_ROWST_PBI0_A9 |\
 694                          ORxS_NUMR_11)
 695
 696 /* With a 16 MB DIMM, the PSDMR is configured as follows:
 697  *
 698  *     - Page Based Interleaving,
 699  *     - Refresh Enable,
 700  *     - Address Multiplexing where A5 is output on A14 pin
 701  *       (A6 on A15, and so on),
 702  *     - use address pins A16-A18 as bank select,
 703  *     - A9 is output on SDA10 during an ACTIVATE command,
 704  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 705  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 706  *       is 3 clocks,
 707  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 708  *       2 clocks,
 709  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 710  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 711  *     - CAS Latency is 2.
 712  */
 713
 714 /*-----------------------------------------------------------------------
 715  * PSDMR - 60x Bus SDRAM Mode Register
 716  *     Ref: Section 10.3.3 on page 10-21
 717  *-----------------------------------------------------------------------
 718  */
 719 #define CONFIG_SYS_PSDMR   (PSDMR_RFEN       |\
 720                      PSDMR_SDAM_A14_IS_A5 |\
 721                      PSDMR_BSMA_A16_A18   |\
 722                      PSDMR_SDA10_PBI0_A9  |\
 723                      PSDMR_RFRC_7_CLK     |\
 724                      PSDMR_PRETOACT_3W    |\
 725                      PSDMR_ACTTORW_2W     |\
 726                      PSDMR_LDOTOPRE_1C    |\
 727                      PSDMR_WRC_1C         |\
 728                      PSDMR_CL_2)
 729 #endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
 730
 731 /* With a 64 MB DIMM, the OR2 is configured as follows:
 732  *
 733  *     - 64 MB
 734  *     - 4 internal banks per device
 735  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 736  *     - 12 row address lines
 737  *     - Back-to-back page mode
 738  *     - Internal bank interleaving within save device enabled
 739  */
 740 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
 741 #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
 742              ORxS_BPD_4         |\
 743              ORxS_ROWST_PBI0_A8     |\
 744              ORxS_NUMR_12)
 745
 746 /* With a 64 MB DIMM, the PSDMR is configured as follows:
 747  *
 748  *     - Page Based Interleaving,
 749  *     - Refresh Enable,
 750  *     - Address Multiplexing where A5 is output on A14 pin
 751  *       (A6 on A15, and so on),
 752  *     - use address pins A14-A16 as bank select,
 753  *     - A9 is output on SDA10 during an ACTIVATE command,
 754  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 755  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 756  *       is 3 clocks,
 757  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 758  *       2 clocks,
 759  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 760  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 761  *     - CAS Latency is 2.
 762  */
 763
 764 /*-----------------------------------------------------------------------
 765  * PSDMR - 60x Bus SDRAM Mode Register
 766  *     Ref: Section 10.3.3 on page 10-21
 767  *-----------------------------------------------------------------------
 768  */
 769 #define CONFIG_SYS_PSDMR   (PSDMR_RFEN       |\
 770                      PSDMR_SDAM_A14_IS_A5 |\
 771                      PSDMR_BSMA_A14_A16   |\
 772                      PSDMR_SDA10_PBI0_A9  |\
 773                      PSDMR_RFRC_7_CLK     |\
 774                      PSDMR_PRETOACT_3W    |\
 775                      PSDMR_ACTTORW_2W     |\
 776                      PSDMR_LDOTOPRE_1C    |\
 777                      PSDMR_WRC_1C         |\
 778                      PSDMR_CL_2)
 779 #endif  /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
 780
 781 #define CONFIG_SYS_PSRT    0x0e
 782 #define CONFIG_SYS_MPTPR   MPTPR_PTP_DIV32
 783
 784
 785 /*-----------------------------------------------------------------------
 786  * BR4 - Base Register
 787  *     Ref: Section 10.3.1 on page 10-14
 788  * OR4 - Option Register
 789  *     Ref: Section 10.3.2 on page 10-18
 790  *-----------------------------------------------------------------------
 791  */
 792 /* Bank 4 - Onboard Memory Mapped IO controller
 793  *
 794  * This expects the onboard IO controller to connected to *CS4 and
 795  * the local bus.
 796  *     - Base address of 0xe0000000
 797  *     - 8 bit port size (local bus only)
 798  *     - Read and write access
 799  *     - GPCM local bus
 800  *     - Not used for atomic operations
 801  *     - No data pipelining is done
 802  *     - Valid
 803  *     - extended hold time
 804  *     - 11 wait states
 805  */
 806
 807 #ifdef CONFIG_SYS_IO_BASE
 808 #  define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_IO_BASE & BRx_BA_MSK)  |\
 809                             BRx_PS_8                   |\
 810                             BRx_MS_GPCM_L              |\
 811                             BRx_V)
 812
 813 #  define CONFIG_SYS_OR4_PRELIM   (ORxG_AM_MSK                |\
 814                             ORxG_SCY_11_CLK            |\
 815                             ORxG_EHTR)
 816 #endif /* CONFIG_SYS_IO_BASE */
 817
 818 /*
 819  * Internal Definitions
 820  *
 821  * Boot Flags
 822  */
 823 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 824 #define BOOTFLAG_WARM   0x02    /* Software reboot           */
 825
 826 #endif  /* __CONFIG_H */