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1 /*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jmonkman@adventnetworks.com>
12 *
13 * (C) Copyright 2001
14 * Advent Networks, Inc. <http://www.adventnetworks.com>
15 * Oliver Brown <obrown@adventnetworks.com>
16 *
17 * SPDX-License-Identifier: GPL-2.0+
18 */
19
20 /*********************************************************************/
21 /* DESCRIPTION:
22 * This file contains the board configuartion for the GW8260 board.
23 *
24 * MODULE DEPENDENCY:
25 * None
26 *
27 * RESTRICTIONS/LIMITATIONS:
28 * None
29 *
30 * Copyright (c) 2001, Advent Networks, Inc.
31 */
32 /*********************************************************************/
33
34 #ifndef __CONFIG_H
35 #define __CONFIG_H
36
37 #define CONFIG_SYS_TEXT_BASE 0x40000000
38
39 /* Enable debug prints */
40 #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
41
42 /* What is the oscillator's (UX2) frequency in Hz? */
43 #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
44
45 /*-----------------------------------------------------------------------
46 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
47 *-----------------------------------------------------------------------
48 * What should MODCK_H be? It is dependent on the oscillator
49 * frequency, MODCK[1-3], and desired CPM and core frequencies.
50 * Here are some example values (all frequencies are in MHz):
51 *
52 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
53 * ------- ---------- --- --- ---- ----- ----- -----
54 * 0x5 0x5 66 133 133 Open Close Open
55 * 0x5 0x6 66 133 166 Open Open Close
56 * 0x5 0x7 66 133 200 Open Open Open
57 * 0x6 0x0 66 133 233 Close Close Close
58 * 0x6 0x1 66 133 266 Close Close Open
59 * 0x6 0x2 66 133 300 Close Open Close
60 */
61 #define CONFIG_SYS_SBC_MODCK_H 0x05
62
63 /* Define this if you want to boot from 0x00000100. If you don't define
64 * this, you will need to program the bootloader to 0xfff00000, and
65 * get the hardware reset config words at 0xfe000000. The simplest
66 * way to do that is to program the bootloader at both addresses.
67 * It is suggested that you just let U-Boot live at 0x00000000.
68 */
69 #define CONFIG_SYS_SBC_BOOT_LOW 1
70
71 /* What should the base address of the main FLASH be and how big is
72 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
73 * The main FLASH is whichever is connected to *CS0. U-Boot expects
74 * this to be the SIMM.
75 */
76 #define CONFIG_SYS_FLASH0_BASE 0x40000000
77 #define CONFIG_SYS_FLASH0_SIZE 8
78
79 /* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
80 * Note: the 'flashchecksum' environment variable must also be set to 'y'.
81 */
82 #define CONFIG_SYS_FLASH_CHECKSUM
83
84 /* What should be the base address of SDRAM DIMM and how big is
85 * it (in Mbytes)?
86 */
87 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
88 #define CONFIG_SYS_SDRAM0_SIZE 64
89
90 /*
91 * DRAM tests
92 * CONFIG_SYS_DRAM_TEST - enables the following tests.
93 *
94 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
95 * Environment variable 'test_dram_data' must be
96 * set to 'y'.
97 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
98 * addressable. Environment variable
99 * 'test_dram_address' must be set to 'y'.
100 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
101 * This test takes about 6 minutes to test 64 MB.
102 * Environment variable 'test_dram_walk' must be
103 * set to 'y'.
104 */
105 #define CONFIG_SYS_DRAM_TEST
106 #if defined(CONFIG_SYS_DRAM_TEST)
107 #define CONFIG_SYS_DRAM_TEST_DATA
108 #define CONFIG_SYS_DRAM_TEST_ADDRESS
109 #define CONFIG_SYS_DRAM_TEST_WALK
110 #endif /* CONFIG_SYS_DRAM_TEST */
111
112 /*
113 * GW8260 with 16 MB DIMM:
114 *
115 * 0x0000 0000 Exception Vector code, 8k
116 * :
117 * 0x0000 1FFF
118 * 0x0000 2000 Free for Application Use
119 * :
120 * :
121 *
122 * :
123 * :
124 * 0x00F5 FF30 Monitor Stack (Growing downward)
125 * Monitor Stack Buffer (0x80)
126 * 0x00F5 FFB0 Board Info Data
127 * 0x00F6 0000 Malloc Arena
128 * : CONFIG_ENV_SECT_SIZE, 256k
129 * : CONFIG_SYS_MALLOC_LEN, 128k
130 * 0x00FC 0000 RAM Copy of Monitor Code
131 * : CONFIG_SYS_MONITOR_LEN, 256k
132 * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
133 */
134
135 /*
136 * GW8260 with 64 MB DIMM:
137 *
138 * 0x0000 0000 Exception Vector code, 8k
139 * :
140 * 0x0000 1FFF
141 * 0x0000 2000 Free for Application Use
142 * :
143 * :
144 *
145 * :
146 * :
147 * 0x03F5 FF30 Monitor Stack (Growing downward)
148 * Monitor Stack Buffer (0x80)
149 * 0x03F5 FFB0 Board Info Data
150 * 0x03F6 0000 Malloc Arena
151 * : CONFIG_ENV_SECT_SIZE, 256k
152 * : CONFIG_SYS_MALLOC_LEN, 128k
153 * 0x03FC 0000 RAM Copy of Monitor Code
154 * : CONFIG_SYS_MONITOR_LEN, 256k
155 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
156 */
157
158
159 /*
160 * select serial console configuration
161 *
162 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
163 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
164 * for SCC).
165 *
166 * if CONFIG_CONS_NONE is defined, then the serial console routines must
167 * defined elsewhere.
168 */
169 #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
170 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
171 #undef CONFIG_CONS_NONE /* define if console on neither */
172 #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
173
174 /*
175 * select ethernet configuration
176 *
177 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
178 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
179 * for FCC)
180 *
181 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
182 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
183 */
184
185 #undef CONFIG_ETHER_ON_SCC
186 #define CONFIG_ETHER_ON_FCC
187 #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
188
189 #ifdef CONFIG_ETHER_ON_SCC
190 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
191 #endif /* CONFIG_ETHER_ON_SCC */
192
193 #ifdef CONFIG_ETHER_ON_FCC
194 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
195 #define CONFIG_MII /* MII PHY management */
196 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
197 /*
198 * Port pins used for bit-banged MII communictions (if applicable).
199 */
200 #define MDIO_PORT 2 /* Port C */
201
202 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
203 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
204 #define MDC_DECLARE MDIO_DECLARE
205
206 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
207 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
208 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
209
210 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
211 else iop->pdat &= ~0x00400000
212
213 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
214 else iop->pdat &= ~0x00200000
215
216 #define MIIDELAY udelay(1)
217 #endif /* CONFIG_ETHER_ON_FCC */
218
219 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
220
221 /*
222 * - Rx-CLK is CLK13
223 * - Tx-CLK is CLK14
224 * - Select bus for bd/buffers (see 28-13)
225 * - Enable Full Duplex in FSMR
226 */
227 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
228 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
229 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
230 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
231
232 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
233
234 /*
235 * - Rx-CLK is CLK15
236 * - Tx-CLK is CLK16
237 * - Select bus for bd/buffers (see 28-13)
238 * - Enable Full Duplex in FSMR
239 */
240 # define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
241 # define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
242 # define CONFIG_SYS_CPMFCR_RAMTYPE 0
243 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
244
245 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
246
247 /* Define this to reserve an entire FLASH sector (256 KB) for
248 * environment variables. Otherwise, the environment will be
249 * put in the same sector as U-Boot, and changing variables
250 * will erase U-Boot temporarily
251 */
252 #define CONFIG_ENV_IN_OWN_SECT
253
254 /* Define to allow the user to overwrite serial and ethaddr */
255 #define CONFIG_ENV_OVERWRITE
256
257 /* What should the console's baud rate be? */
258 #define CONFIG_BAUDRATE 115200
259
260 /* Ethernet MAC address - This is set to all zeros to force an
261 * an error if we use BOOTP without setting
262 * the MAC address
263 */
264 #define CONFIG_ETHADDR 00:00:00:00:00:00
265
266 /* Set to a positive value to delay for running BOOTCOMMAND */
267 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
268
269 /* Be selective on what keys can delay or stop the autoboot process
270 * To stop use: " "
271 */
272 #define CONFIG_AUTOBOOT_KEYED
273 #define CONFIG_AUTOBOOT_PROMPT \
274 "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
275 #define CONFIG_AUTOBOOT_STOP_STR " "
276 #undef CONFIG_AUTOBOOT_DELAY_STR
277 #define DEBUG_BOOTKEYS 0
278
279 /*
280 * BOOTP options
281 */
282 #define CONFIG_BOOTP_SUBNETMASK
283 #define CONFIG_BOOTP_GATEWAY
284 #define CONFIG_BOOTP_HOSTNAME
285 #define CONFIG_BOOTP_BOOTPATH
286
287 #define CONFIG_BOOTP_BOOTFILESIZE
288 #define CONFIG_BOOTP_DNS
289
290 /* undef this to save memory */
291 #define CONFIG_SYS_LONGHELP
292
293 /* Monitor Command Prompt */
294 #define CONFIG_SYS_PROMPT "=> "
295
296
297 /*
298 * Command line configuration.
299 */
300 #include <config_cmd_default.h>
301
302 #define CONFIG_CMD_BEDBUG
303 #define CONFIG_CMD_ELF
304 #define CONFIG_CMD_ASKENV
305 #define CONFIG_CMD_REGINFO
306 #define CONFIG_CMD_IMMAP
307 #define CONFIG_CMD_MII
308
309 #undef CONFIG_CMD_KGDB
310
311
312 /* Where do the internal registers live? */
313 #define CONFIG_SYS_IMMR 0xf0000000
314
315 /* Use the HUSH parser */
316 #define CONFIG_SYS_HUSH_PARSER
317 #ifdef CONFIG_SYS_HUSH_PARSER
318 #endif
319
320 /* What is the address of IO controller */
321 #define CONFIG_SYS_IO_BASE 0xe0000000
322
323 /*****************************************************************************
324 *
325 * You should not have to modify any of the following settings
326 *
327 *****************************************************************************/
328
329 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
330 #define CONFIG_GW8260 1 /* on an GW8260 Board */
331 #define CONFIG_CPM2 1 /* Has a CPM2 */
332
333 /*
334 * Miscellaneous configurable options
335 */
336 #if defined(CONFIG_CMD_KGDB)
337 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
338 #else
339 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
340 #endif
341
342 /* Print Buffer Size */
343 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
344
345 #define CONFIG_SYS_MAXARGS 8 /* max number of command args */
346
347 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
348
349 /* Convert clocks to MHZ when passing board info to kernel.
350 * This must be defined for eariler 2.4 kernels (~2.4.4).
351 */
352 #define CONFIG_CLOCKS_IN_MHZ
353
354 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
355 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
356
357
358 /* memtest works from the end of the exception vector table
359 * to the end of the DRAM less monitor and malloc area
360 */
361 #define CONFIG_SYS_MEMTEST_START 0x2000
362
363 #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
364
365 #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
366 + CONFIG_SYS_MALLOC_LEN \
367 + CONFIG_ENV_SECT_SIZE \
368 + CONFIG_SYS_STACK_USAGE )
369
370 #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
371 - CONFIG_SYS_MEM_END_USAGE )
372
373 /*
374 * Low Level Configuration Settings
375 * (address mappings, register initial values, etc.)
376 * You should know what you are doing if you make changes here.
377 */
378
379 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
380 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
381 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
382 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
383
384 /*-----------------------------------------------------------------------
385 * Hard Reset Configuration Words
386 */
387 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
388 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
389 #else
390 # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
391 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
392
393 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
394 #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
395 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
396 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
397
398 #define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \
399 HRCW_DPPC11 | \
400 CONFIG_SYS_SBC_HRCW_IMMR | \
401 HRCW_MMR00 | \
402 HRCW_LBPC11 | \
403 HRCW_APPC10 | \
404 HRCW_CS10PC00 | \
405 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
406 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
407
408 /* no slaves */
409 #define CONFIG_SYS_HRCW_SLAVE1 0
410 #define CONFIG_SYS_HRCW_SLAVE2 0
411 #define CONFIG_SYS_HRCW_SLAVE3 0
412 #define CONFIG_SYS_HRCW_SLAVE4 0
413 #define CONFIG_SYS_HRCW_SLAVE5 0
414 #define CONFIG_SYS_HRCW_SLAVE6 0
415 #define CONFIG_SYS_HRCW_SLAVE7 0
416
417 /*-----------------------------------------------------------------------
418 * Definitions for initial stack pointer and data area (in DPRAM)
419 */
420 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
421 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
422 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
423 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
424
425 /*-----------------------------------------------------------------------
426 * Start addresses for the final memory configuration
427 * (Set up by the startup code)
428 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
429 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
430 */
431 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
432
433 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
434 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
435
436 /*
437 * For booting Linux, the board info and command line data
438 * have to be in the first 8 MB of memory, since this is
439 * the maximum mapped by the Linux kernel during initialization.
440 */
441 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* Initial Memory map for Linux */
442
443 /*-----------------------------------------------------------------------
444 * FLASH and environment organization
445 */
446 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
447 #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
448
449 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
450 #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
451
452 #define CONFIG_ENV_IS_IN_FLASH 1
453
454 #ifdef CONFIG_ENV_IN_OWN_SECT
455 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + (256 * 1024))
456 # define CONFIG_ENV_SECT_SIZE (256 * 1024)
457 #else
458 # define CONFIG_ENV_SIZE (16 * 1024)/* Size of Environment Sector */
459 # define CONFIG_ENV_ADD ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
460 # define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size */
461 #endif /* CONFIG_ENV_IN_OWN_SECT */
462
463 /*-----------------------------------------------------------------------
464 * Cache Configuration
465 */
466 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
467
468 #if defined(CONFIG_CMD_KGDB)
469 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
470 #endif
471
472 /*-----------------------------------------------------------------------
473 * HIDx - Hardware Implementation-dependent Registers 2-11
474 *-----------------------------------------------------------------------
475 * HID0 also contains cache control - initially enable both caches and
476 * invalidate contents, then the final state leaves only the instruction
477 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
478 * but Soft reset does not.
479 *
480 * HID1 has only read-only information - nothing to set.
481 */
482 #define CONFIG_SYS_HID0_INIT (HID0_ICE |\
483 HID0_DCE |\
484 HID0_ICFI |\
485 HID0_DCI |\
486 HID0_IFEM |\
487 HID0_ABE)
488
489 #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
490 HID0_IFEM |\
491 HID0_ABE |\
492 HID0_EMCP)
493 #define CONFIG_SYS_HID2 0
494
495 /*-----------------------------------------------------------------------
496 * RMR - Reset Mode Register
497 *-----------------------------------------------------------------------
498 */
499 #define CONFIG_SYS_RMR 0
500
501 /*-----------------------------------------------------------------------
502 * BCR - Bus Configuration 4-25
503 *-----------------------------------------------------------------------
504 */
505 #define CONFIG_SYS_BCR (BCR_ETM)
506
507 /*-----------------------------------------------------------------------
508 * SIUMCR - SIU Module Configuration 4-31
509 *-----------------------------------------------------------------------
510 */
511 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
512 SIUMCR_L2CPC00 |\
513 SIUMCR_APPC10 |\
514 SIUMCR_MMR00)
515
516
517 /*-----------------------------------------------------------------------
518 * SYPCR - System Protection Control 11-9
519 * SYPCR can only be written once after reset!
520 *-----------------------------------------------------------------------
521 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
522 */
523 #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
524 SYPCR_BMT |\
525 SYPCR_PBME |\
526 SYPCR_LBME |\
527 SYPCR_SWRI |\
528 SYPCR_SWP)
529
530 /*-----------------------------------------------------------------------
531 * TMCNTSC - Time Counter Status and Control 4-40
532 *-----------------------------------------------------------------------
533 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
534 * and enable Time Counter
535 */
536 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
537 TMCNTSC_ALR |\
538 TMCNTSC_TCF |\
539 TMCNTSC_TCE)
540
541 /*-----------------------------------------------------------------------
542 * PISCR - Periodic Interrupt Status and Control 4-42
543 *-----------------------------------------------------------------------
544 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
545 * Periodic timer
546 */
547 #define CONFIG_SYS_PISCR (PISCR_PS |\
548 PISCR_PTF |\
549 PISCR_PTE)
550
551 /*-----------------------------------------------------------------------
552 * SCCR - System Clock Control 9-8
553 *-----------------------------------------------------------------------
554 */
555 #define CONFIG_SYS_SCCR 0
556
557 /*-----------------------------------------------------------------------
558 * RCCR - RISC Controller Configuration 13-7
559 *-----------------------------------------------------------------------
560 */
561 #define CONFIG_SYS_RCCR 0
562
563 /*
564 * Initialize Memory Controller:
565 *
566 * Bank Bus Machine PortSz Device
567 * ---- --- ------- ------ ------
568 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB)
569 * 1 60x GPCM 32 bit unused
570 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
571 * 3 60x SDRAM 64 bit unused
572 * 4 Local GPCM 8 bit IO (on board - 64k)
573 * 5 60x GPCM 8 bit unused
574 * 6 60x GPCM 8 bit unused
575 * 7 60x GPCM 8 bit unused
576 *
577 */
578
579 /*-----------------------------------------------------------------------
580 * BR0 - Base Register
581 * Ref: Section 10.3.1 on page 10-14
582 * OR0 - Option Register
583 * Ref: Section 10.3.2 on page 10-18
584 *-----------------------------------------------------------------------
585 */
586
587 /* Bank 0,1 - FLASH SIMM
588 *
589 * This expects the FLASH SIMM to be connected to *CS0
590 * It consists of 4 AM29F016D parts.
591 *
592 * Note: For the 8 MB SIMM, *CS1 is unused.
593 */
594
595 /* BR0 is configured as follows:
596 *
597 * - Base address of 0x40000000
598 * - 32 bit port size
599 * - Data errors checking is disabled
600 * - Read and write access
601 * - GPCM 60x bus
602 * - Access are handled by the memory controller according to MSEL
603 * - Not used for atomic operations
604 * - No data pipelining is done
605 * - Valid
606 */
607 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
608 BRx_PS_32 |\
609 BRx_MS_GPCM_P |\
610 BRx_V)
611
612 /* OR0 is configured as follows:
613 *
614 * - 8 MB
615 * - *BCTL0 is asserted upon access to the current memory bank
616 * - *CW / *WE are negated a quarter of a clock earlier
617 * - *CS is output at the same time as the address lines
618 * - Uses a clock cycle length of 5
619 * - *PSDVAL is generated internally by the memory controller
620 * unless *GTA is asserted earlier externally.
621 * - Relaxed timing is generated by the GPCM for accesses
622 * initiated to this memory region.
623 * - One idle clock is inserted between a read access from the
624 * current bank and the next access.
625 */
626 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
627 ORxG_CSNT |\
628 ORxG_ACS_DIV1 |\
629 ORxG_SCY_5_CLK |\
630 ORxG_TRLX |\
631 ORxG_EHTR)
632
633 /*-----------------------------------------------------------------------
634 * BR2 - Base Register
635 * Ref: Section 10.3.1 on page 10-14
636 * OR2 - Option Register
637 * Ref: Section 10.3.2 on page 10-16
638 *-----------------------------------------------------------------------
639 */
640
641 /* Bank 2 - SDRAM DIMM
642 *
643 * 16MB DIMM: P/N
644 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST or
645 * MT4LSDT864AG-10EB1 (Micron)
646 *
647 * Note: *CS3 is unused for this DIMM
648 */
649
650 /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
651 *
652 * - Base address of 0x00000000
653 * - 64 bit port size (60x bus only)
654 * - Data errors checking is disabled
655 * - Read and write access
656 * - SDRAM 60x bus
657 * - Access are handled by the memory controller according to MSEL
658 * - Not used for atomic operations
659 * - No data pipelining is done
660 * - Valid
661 */
662 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
663 BRx_PS_64 |\
664 BRx_MS_SDRAM_P |\
665 BRx_V)
666
667 /* With a 16 MB DIMM, the OR2 is configured as follows:
668 *
669 * - 16 MB
670 * - 2 internal banks per device
671 * - Row start address bit is A9 with PSDMR[PBI] = 0
672 * - 11 row address lines
673 * - Back-to-back page mode
674 * - Internal bank interleaving within save device enabled
675 */
676 #if (CONFIG_SYS_SDRAM0_SIZE == 16)
677 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
678 ORxS_BPD_2 |\
679 ORxS_ROWST_PBI0_A9 |\
680 ORxS_NUMR_11)
681
682 /* With a 16 MB DIMM, the PSDMR is configured as follows:
683 *
684 * - Page Based Interleaving,
685 * - Refresh Enable,
686 * - Address Multiplexing where A5 is output on A14 pin
687 * (A6 on A15, and so on),
688 * - use address pins A16-A18 as bank select,
689 * - A9 is output on SDA10 during an ACTIVATE command,
690 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
691 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
692 * is 3 clocks,
693 * - earliest timing for READ/WRITE command after ACTIVATE command is
694 * 2 clocks,
695 * - earliest timing for PRECHARGE after last data was read is 1 clock,
696 * - earliest timing for PRECHARGE after last data was written is 1 clock,
697 * - CAS Latency is 2.
698 */
699
700 /*-----------------------------------------------------------------------
701 * PSDMR - 60x Bus SDRAM Mode Register
702 * Ref: Section 10.3.3 on page 10-21
703 *-----------------------------------------------------------------------
704 */
705 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
706 PSDMR_SDAM_A14_IS_A5 |\
707 PSDMR_BSMA_A16_A18 |\
708 PSDMR_SDA10_PBI0_A9 |\
709 PSDMR_RFRC_7_CLK |\
710 PSDMR_PRETOACT_3W |\
711 PSDMR_ACTTORW_2W |\
712 PSDMR_LDOTOPRE_1C |\
713 PSDMR_WRC_1C |\
714 PSDMR_CL_2)
715 #endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
716
717 /* With a 64 MB DIMM, the OR2 is configured as follows:
718 *
719 * - 64 MB
720 * - 4 internal banks per device
721 * - Row start address bit is A8 with PSDMR[PBI] = 0
722 * - 12 row address lines
723 * - Back-to-back page mode
724 * - Internal bank interleaving within save device enabled
725 */
726 #if (CONFIG_SYS_SDRAM0_SIZE == 64)
727 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
728 ORxS_BPD_4 |\
729 ORxS_ROWST_PBI0_A8 |\
730 ORxS_NUMR_12)
731
732 /* With a 64 MB DIMM, the PSDMR is configured as follows:
733 *
734 * - Page Based Interleaving,
735 * - Refresh Enable,
736 * - Address Multiplexing where A5 is output on A14 pin
737 * (A6 on A15, and so on),
738 * - use address pins A14-A16 as bank select,
739 * - A9 is output on SDA10 during an ACTIVATE command,
740 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
741 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
742 * is 3 clocks,
743 * - earliest timing for READ/WRITE command after ACTIVATE command is
744 * 2 clocks,
745 * - earliest timing for PRECHARGE after last data was read is 1 clock,
746 * - earliest timing for PRECHARGE after last data was written is 1 clock,
747 * - CAS Latency is 2.
748 */
749
750 /*-----------------------------------------------------------------------
751 * PSDMR - 60x Bus SDRAM Mode Register
752 * Ref: Section 10.3.3 on page 10-21
753 *-----------------------------------------------------------------------
754 */
755 #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
756 PSDMR_SDAM_A14_IS_A5 |\
757 PSDMR_BSMA_A14_A16 |\
758 PSDMR_SDA10_PBI0_A9 |\
759 PSDMR_RFRC_7_CLK |\
760 PSDMR_PRETOACT_3W |\
761 PSDMR_ACTTORW_2W |\
762 PSDMR_LDOTOPRE_1C |\
763 PSDMR_WRC_1C |\
764 PSDMR_CL_2)
765 #endif /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
766
767 #define CONFIG_SYS_PSRT 0x0e
768 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
769
770
771 /*-----------------------------------------------------------------------
772 * BR4 - Base Register
773 * Ref: Section 10.3.1 on page 10-14
774 * OR4 - Option Register
775 * Ref: Section 10.3.2 on page 10-18
776 *-----------------------------------------------------------------------
777 */
778 /* Bank 4 - Onboard Memory Mapped IO controller
779 *
780 * This expects the onboard IO controller to connected to *CS4 and
781 * the local bus.
782 * - Base address of 0xe0000000
783 * - 8 bit port size (local bus only)
784 * - Read and write access
785 * - GPCM local bus
786 * - Not used for atomic operations
787 * - No data pipelining is done
788 * - Valid
789 * - extended hold time
790 * - 11 wait states
791 */
792
793 #ifdef CONFIG_SYS_IO_BASE
794 # define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
795 BRx_PS_8 |\
796 BRx_MS_GPCM_L |\
797 BRx_V)
798
799 # define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
800 ORxG_SCY_11_CLK |\
801 ORxG_EHTR)
802 #endif /* CONFIG_SYS_IO_BASE */
803 #endif /* __CONFIG_H */
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