include/configs/hermes.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1       /* This is a MPC860T CPU        */
  21 #define CONFIG_HERMES           1       /* ...on a HERMES-PRO board     */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  24
  25 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  26 #undef  CONFIG_8xx_CONS_SMC2
  27 #undef  CONFIG_8xx_CONS_NONE
  28 #define CONFIG_BAUDRATE         9600
  29 #if 0
  30 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  31 #else
  32 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  33 #endif
  34
  35 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  36
  37 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  38
  39 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* Show boot progress on LEDs   */
  40
  41 #undef  CONFIG_BOOTARGS
  42 #define CONFIG_BOOTCOMMAND                                                      \
  43         "bootp; "                                                               \
  44         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  45         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  46         "bootm"
  47
  48 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  49 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  50
  51 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  52
  53
  54 /*
  55  * Command line configuration.
  56  */
  57 #include <config_cmd_default.h>
  58
  59
  60 /*
  61  * BOOTP options
  62  */
  63 #define CONFIG_BOOTP_SUBNETMASK
  64 #define CONFIG_BOOTP_GATEWAY
  65 #define CONFIG_BOOTP_HOSTNAME
  66 #define CONFIG_BOOTP_BOOTPATH
  67
  68
  69 /*
  70  * Miscellaneous configurable options
  71  */
  72 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  73 #if defined(CONFIG_CMD_KGDB)
  74 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  75 #else
  76 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  77 #endif
  78 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  79 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  80 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  81
  82 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
  83 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
  84
  85 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
  86
  87 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
  88
  89 #define CONFIG_SYS_ALLOC_DPRAM          1       /* use allocation routines      */
  90 /*
  91  * Low Level Configuration Settings
  92  * (address mappings, register initial values, etc.)
  93  * You should know what you are doing if you make changes here.
  94  */
  95 /*-----------------------------------------------------------------------
  96  * Internal Memory Mapped Register
  97  */
  98 #define CONFIG_SYS_IMMR         0xFF000000      /* Non-Standard value!  */
  99
 100 /*-----------------------------------------------------------------------
 101  * Definitions for initial stack pointer and data area (in DPRAM)
 102  */
 103 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 104 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 105 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 106 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 107
 108 /*-----------------------------------------------------------------------
 109  * Start addresses for the final memory configuration
 110  * (Set up by the startup code)
 111  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 112  */
 113 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 114 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 115 #ifdef  DEBUG
 116 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 117 #else
 118 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 119 #endif
 120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 121 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 122
 123 /*
 124  * For booting Linux, the board info and command line data
 125  * have to be in the first 8 MB of memory, since this is
 126  * the maximum mapped by the Linux kernel during initialization.
 127  */
 128 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 129 /*-----------------------------------------------------------------------
 130  * FLASH organization
 131  */
 132 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 133 #define CONFIG_SYS_MAX_FLASH_SECT       124     /* max number of sectors on one chip    */
 134
 135 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 136 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 137
 138 #define CONFIG_ENV_IS_IN_FLASH  1
 139 #define CONFIG_ENV_OFFSET               0x4000  /*   Offset   of Environment Sector     */
 140 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 141 /*-----------------------------------------------------------------------
 142  * Cache Configuration
 143  */
 144 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 145 #if defined(CONFIG_CMD_KGDB)
 146 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 147 #endif
 148
 149 /*-----------------------------------------------------------------------
 150  * SYPCR - System Protection Control                            11-9
 151  * SYPCR can only be written once after reset!
 152  *-----------------------------------------------------------------------
 153  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 154  * +0x0004
 155  */
 156 #if defined(CONFIG_WATCHDOG)
 157 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 158                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 159 #else
 160 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 161 #endif
 162
 163 /*-----------------------------------------------------------------------
 164  * SIUMCR - SIU Module Configuration                            11-6
 165  *-----------------------------------------------------------------------
 166  * +0x0000 => 0x000000C0
 167  */
 168 #define CONFIG_SYS_SIUMCR       0
 169
 170 /*-----------------------------------------------------------------------
 171  * TBSCR - Time Base Status and Control                         11-26
 172  *-----------------------------------------------------------------------
 173  * Clear Reference Interrupt Status, Timebase freezing enabled
 174  * +0x0200 => 0x00C2
 175  */
 176 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 177
 178 /*-----------------------------------------------------------------------
 179  * PISCR - Periodic Interrupt Status and Control                11-31
 180  *-----------------------------------------------------------------------
 181  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 182  * +0x0240 => 0x0082
 183  */
 184 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 185
 186 /*-----------------------------------------------------------------------
 187  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 188  *-----------------------------------------------------------------------
 189  * Reset PLL lock status sticky bit, timer expired status bit and timer
 190  * interrupt status bit, set PLL multiplication factor !
 191  */
 192 /* +0x0286 => 0x00B0D0C0 */
 193 #define CONFIG_SYS_PLPRCR                                                       \
 194                 (       (11 << PLPRCR_MF_SHIFT) |                       \
 195                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 196                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 197                         PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 198                 )
 199
 200 /*-----------------------------------------------------------------------
 201  * SCCR - System Clock and reset Control Register               15-27
 202  *-----------------------------------------------------------------------
 203  * Set clock output, timebase and RTC source and divider,
 204  * power management and some other internal clocks
 205  */
 206 #define SCCR_MASK       SCCR_EBDF11
 207 /* +0x0282 => 0x03800000 */
 208 #define CONFIG_SYS_SCCR (SCCR_COM00     |   SCCR_TBS      |     \
 209                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 210                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 211                          SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 212                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 213                          SCCR_DFNH000)
 214
 215 /*-----------------------------------------------------------------------
 216  * RTCSC - Real-Time Clock Status and Control Register          11-27
 217  *-----------------------------------------------------------------------
 218  */
 219 /* +0x0220 => 0x00C3 */
 220 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 221
 222
 223 /*-----------------------------------------------------------------------
 224  * RCCR - RISC Controller Configuration Register                19-4
 225  *-----------------------------------------------------------------------
 226  */
 227 /* +0x09C4 => TIMEP=1 */
 228 #define CONFIG_SYS_RCCR 0x0100
 229
 230 /*-----------------------------------------------------------------------
 231  * RMDS - RISC Microcode Development Support Control Register
 232  *-----------------------------------------------------------------------
 233  */
 234 #define CONFIG_SYS_RMDS 0
 235
 236 /*-----------------------------------------------------------------------
 237  *
 238  *-----------------------------------------------------------------------
 239  *
 240  */
 241 #define CONFIG_SYS_DER  0
 242
 243 /*
 244  * Init Memory Controller:
 245  *
 246  * BR0 and OR0 (FLASH)
 247  */
 248
 249 #define FLASH_BASE0_PRELIM      0xFE000000      /* FLASH bank #0        */
 250
 251 /* used to re-map FLASH
 252  * restrict access enough to keep SRAM working (if any)
 253  * but not too much to meddle with FLASH accesses
 254  */
 255 /* allow for max 4 MB of Flash */
 256 #define CONFIG_SYS_REMAP_OR_AM          0xFFC00000      /* OR addr mask */
 257 #define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000      /* OR addr mask */
 258
 259 /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0        */
 260 #define CONFIG_SYS_OR_TIMING_FLASH      ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
 261                                  OR_SCY_5_CLK | OR_TRLX)
 262
 263 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 264 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 265 /* 8 bit, bank valid */
 266 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 267
 268 /*
 269  * BR1/OR1 - SDRAM
 270  *
 271  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 272  */
 273 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM bank */
 274 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 275 #define SDRAM_TIMING            0x00000A00      /* SDRAM-Timing */
 276
 277 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 278
 279 #define CONFIG_SYS_OR1_PRELIM   (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 280 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 281
 282 /*
 283  * BR2/OR2 - HPRO2: PEB2256   @ 0xE0000000, 8 Bit wide
 284  */
 285 #define HPRO2_BASE              0xE0000000
 286 #define HPRO2_OR_AM             0xFFFF8000
 287 #define HPRO2_TIMING            0x00000934
 288
 289 #define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
 290 #define CONFIG_SYS_BR2  ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 291
 292 /*
 293  * BR3/OR3: not used
 294  * BR4/OR4: not used
 295  * BR5/OR5: not used
 296  * BR6/OR6: not used
 297  * BR7/OR7: not used
 298  */
 299
 300 /*
 301  * MAMR settings for SDRAM
 302  */
 303
 304 /* periodic timer for refresh */
 305 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz       */
 306
 307 /* 8 column SDRAM */
 308 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 309                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 310                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 311 /* 9 column SDRAM */
 312 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 313                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 314                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 315 #endif  /* __CONFIG_H */