include/configs/highbank.h

   1 /*
   2  * Copyright 2010-2011 Calxeda, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <config_distro_defaults.h>
  11
  12 #define CONFIG_SYS_DCACHE_OFF
  13
  14 #define CONFIG_SYS_BOOTMAPSZ            (16 << 20)
  15
  16 #define CONFIG_SYS_TIMER_RATE           (150000000/256)
  17 #define CONFIG_SYS_TIMER_COUNTER        (0xFFF34000 + 0x4)
  18 #define CONFIG_SYS_TIMER_COUNTS_DOWN
  19
  20 /*
  21  * Size of malloc() pool
  22  */
  23 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
  24
  25 #define CONFIG_PL011_CLOCK              150000000
  26 #define CONFIG_PL01x_PORTS              { (void *)(0xFFF36000) }
  27 #define CONFIG_CONS_INDEX               0
  28
  29 #define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
  30 #define CONFIG_SYS_BOOTCOUNT_LE         /* Use little-endian accessors */
  31 #define CONFIG_SYS_BOOTCOUNT_ADDR       0xfff3cf0c
  32
  33 #define CONFIG_MISC_INIT_R
  34 #define CONFIG_SCSI_AHCI_PLAT
  35 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     5
  36 #define CONFIG_SYS_SCSI_MAX_LUN         1
  37 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  38                                         CONFIG_SYS_SCSI_MAX_LUN)
  39
  40 #define CONFIG_CALXEDA_XGMAC
  41
  42 /*
  43  * Command line configuration.
  44  */
  45
  46 #define CONFIG_BOOT_RETRY_TIME          -1
  47 #define CONFIG_RESET_TO_RETRY
  48
  49 /*
  50  * Miscellaneous configurable options
  51  */
  52 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
  53 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  54
  55 #define CONFIG_SYS_LOAD_ADDR            0x800000
  56 #define CONFIG_SYS_64BIT_LBA
  57
  58 /*-----------------------------------------------------------------------
  59  * Physical Memory Map
  60  * The DRAM is already setup, so do not touch the DT node later.
  61  */
  62 #define CONFIG_NR_DRAM_BANKS            0
  63 #define PHYS_SDRAM_1_SIZE               (4089 << 20)
  64 #define CONFIG_SYS_MEMTEST_START        0x100000
  65 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_1_SIZE - 0x100000)
  66
  67 /* Environment data setup
  68 */
  69 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xfff88000      /* NVRAM base address */
  70 #define CONFIG_SYS_NVRAM_SIZE           0x8000          /* NVRAM size */
  71 #define CONFIG_ENV_SIZE                 0x2000          /* Size of Environ */
  72 #define CONFIG_ENV_ADDR                 CONFIG_SYS_NVRAM_BASE_ADDR
  73
  74 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  75 #define CONFIG_SYS_INIT_SP_ADDR         0x01000000
  76 #define CONFIG_SKIP_LOWLEVEL_INIT
  77
  78 #endif