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[people/ms/u-boot.git] / include / configs / icon.h
1 /*
2 * (C) Copyright 2009-2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * icon.h - configuration for Mosaixtech ICON (440SPe)
10 */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*
16 * High Level Configuration Options
17 */
18 #define CONFIG_ICON 1 /* Board is icon */
19 #define CONFIG_4xx 1 /* ... PPC4xx family */
20 #define CONFIG_440 1 /* ... PPC440 family */
21 #define CONFIG_440SPE 1 /* Specifc SPe support */
22
23 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
24
25 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
26 #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
27
28 /*
29 * Include common defines/options for all AMCC eval boards
30 */
31 #define CONFIG_HOSTNAME icon
32 #include "amcc-common.h"
33
34 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
35 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
36
37 /*
38 * Base addresses -- Note these are effective addresses where the
39 * actual resources get mapped (not physical addresses)
40 */
41 #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */
42 #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
43
44 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
45 #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
46 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
47
48 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
49 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */
50 #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
51
52 #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
53 #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
54 #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
55 #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
56 #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
57 #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
58
59 /* base address of inbound PCIe window */
60 #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
61
62 /* System RAM mapped to PCI space */
63 #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
64 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
65 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
66
67 #define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */
68 #define CONFIG_SYS_ACE_BASE_PHYS_H 0x4
69 #define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000
70
71 #define CONFIG_SYS_FLASH_SIZE (64 << 20)
72 #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
73 #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
74 #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000
75 #define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
76 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
77
78 /*
79 * Initial RAM & stack pointer (placed in internal SRAM)
80 */
81 #define CONFIG_SYS_TEMP_STACK_OCM 1
82 #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
83 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */
84 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* size of used area */
85
86 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
87 GENERATED_GBL_DATA_SIZE)
88 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
89
90 /*
91 * Serial Port
92 */
93 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
94 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
95
96 /*
97 * DDR2 SDRAM
98 */
99 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
100 #define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */
101 #define CONFIG_DDR_ECC /* with ECC support */
102 #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
103
104 /*
105 * I2C
106 */
107 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
108
109 #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
110
111 #define CONFIG_SYS_I2C_MULTI_EEPROMS
112 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
113 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
114 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
115 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
116
117 /* I2C bootstrap EEPROM */
118 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
119 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
120 #define CONFIG_4xx_CONFIG_BLOCKSIZE 8
121
122 /* I2C RTC */
123 #define CONFIG_RTC_M41T11
124 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
125 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
126 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
127
128 /*
129 * Video options
130 */
131 #define CONFIG_VIDEO
132
133 #ifdef CONFIG_VIDEO
134 #define CONFIG_VIDEO_SM501
135 #define CONFIG_VIDEO_SM501_32BPP
136 #define CONFIG_VIDEO_SM501_PCI
137 #define VIDEO_FB_LITTLE_ENDIAN
138 #define CONFIG_CFB_CONSOLE
139 #define CONFIG_VIDEO_LOGO
140 #define CONFIG_CONSOLE_EXTRA_INFO
141 #define CONFIG_VGA_AS_SINGLE_DEVICE
142 #define CONFIG_VIDEO_SW_CURSOR
143 #define CONFIG_VIDEO_BMP_RLE8
144 #define CONFIG_SPLASH_SCREEN
145 #define CFG_CONSOLE_IS_IN_ENV
146 #endif
147
148 /*
149 * Environment
150 */
151 #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
152
153 /*
154 * Default environment variables
155 */
156 #define CONFIG_EXTRA_ENV_SETTINGS \
157 CONFIG_AMCC_DEF_ENV \
158 CONFIG_AMCC_DEF_ENV_POWERPC \
159 CONFIG_AMCC_DEF_ENV_NOR_UPD \
160 "kernel_addr=fc000000\0" \
161 "fdt_addr=fc1e0000\0" \
162 "ramdisk_addr=fc200000\0" \
163 "pciconfighost=1\0" \
164 "pcie_mode=RP:RP:RP\0" \
165 ""
166
167 /*
168 * Commands additional to the ones defined in amcc-common.h
169 */
170 #define CONFIG_CMD_CHIP_CONFIG
171 #define CONFIG_CMD_DATE
172 #define CONFIG_CMD_EXT2
173 #define CONFIG_CMD_FAT
174 #define CONFIG_CMD_PCI
175 #define CONFIG_CMD_SDRAM
176 #define CONFIG_CMD_SNTP
177 #ifdef CONFIG_VIDEO
178 #define CONFIG_CMD_BMP
179 #endif
180
181 #define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */
182 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
183 #define CONFIG_HAS_ETH0
184 #define CONFIG_PHY_RESET /* reset phy upon startup */
185 #define CONFIG_PHY_RESET_DELAY 1000
186 #define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */
187 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */
188
189 /*
190 * FLASH related
191 */
192 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
193 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
194 #define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
195 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
196
197 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
198 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */
199 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/
200
201 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
203
204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
205 #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */
206
207 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
208 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
209 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */
210
211 /* Address and size of Redundant Environment Sector */
212 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
213 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
214
215 /*
216 * PCI stuff
217 */
218 /* General PCI */
219 #define CONFIG_PCI /* include pci support */
220 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
221 #define CONFIG_PCI_PNP /* do pci plug-and-play */
222 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
223 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
224 #define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/
225
226 /* Board-specific PCI */
227 #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
228 #undef CONFIG_SYS_PCI_MASTER_INIT
229
230 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
231 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
232
233 /*
234 * Xilinx System ACE support
235 */
236 #define CONFIG_SYSTEMACE /* Enable SystemACE support */
237 #define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
238 #define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
239 #define CONFIG_DOS_PARTITION
240
241 /*
242 * External Bus Controller (EBC) Setup
243 */
244
245 /* Memory Bank 0 (Flash) initialization */
246 #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
247 EBC_BXAP_TWT_ENCODE(7) | \
248 EBC_BXAP_BCE_DISABLE | \
249 EBC_BXAP_BCT_2TRANS | \
250 EBC_BXAP_CSN_ENCODE(0) | \
251 EBC_BXAP_OEN_ENCODE(0) | \
252 EBC_BXAP_WBN_ENCODE(0) | \
253 EBC_BXAP_WBF_ENCODE(0) | \
254 EBC_BXAP_TH_ENCODE(0) | \
255 EBC_BXAP_RE_DISABLED | \
256 EBC_BXAP_SOR_DELAYED | \
257 EBC_BXAP_BEM_WRITEONLY | \
258 EBC_BXAP_PEN_DISABLED)
259 #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
260 EBC_BXCR_BS_64MB | \
261 EBC_BXCR_BU_RW | \
262 EBC_BXCR_BW_16BIT)
263
264 /* Memory Bank 1 (Xilinx System ACE controller) initialization */
265 #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
266 EBC_BXAP_TWT_ENCODE(4) | \
267 EBC_BXAP_BCE_DISABLE | \
268 EBC_BXAP_BCT_2TRANS | \
269 EBC_BXAP_CSN_ENCODE(0) | \
270 EBC_BXAP_OEN_ENCODE(0) | \
271 EBC_BXAP_WBN_ENCODE(0) | \
272 EBC_BXAP_WBF_ENCODE(0) | \
273 EBC_BXAP_TH_ENCODE(0) | \
274 EBC_BXAP_RE_DISABLED | \
275 EBC_BXAP_SOR_NONDELAYED | \
276 EBC_BXAP_BEM_WRITEONLY | \
277 EBC_BXAP_PEN_DISABLED)
278 #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \
279 EBC_BXCR_BS_1MB | \
280 EBC_BXCR_BU_RW | \
281 EBC_BXCR_BW_16BIT)
282
283 /*
284 * Initialize EBC CONFIG -
285 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
286 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
287 */
288 #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
289 EBC_CFG_PTD_ENABLE | \
290 EBC_CFG_RTC_16PERCLK | \
291 EBC_CFG_ATC_PREVIOUS | \
292 EBC_CFG_DTC_PREVIOUS | \
293 EBC_CFG_CTC_PREVIOUS | \
294 EBC_CFG_OEO_PREVIOUS | \
295 EBC_CFG_EMC_DEFAULT | \
296 EBC_CFG_PME_DISABLE | \
297 EBC_CFG_PR_16)
298
299 /*
300 * GPIO Setup
301 */
302 #define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
303 #define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
304 #define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
305 #define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
306
307 #define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
308 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
309 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
310 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
311 #define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
312 #define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
313 #define CONFIG_SYS_GPIO_ODR 0
314
315 #endif /* __CONFIG_H */