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1 /*
2 * (C) Copyright 2004
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
6 *
7 * Configuration settings for the LogicPD i.MX31 Litekit board.
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 #include <asm/arch/imx-regs.h>
16
17 /* High Level Configuration Options */
18 #define CONFIG_MX31 1 /* This is a mx31 */
19 #define CONFIG_MX31_CLK32 32000
20
21 #define CONFIG_DISPLAY_CPUINFO
22 #define CONFIG_DISPLAY_BOARDINFO
23
24 #define CONFIG_SYS_TEXT_BASE 0xa0000000
25
26 #define CONFIG_MACH_TYPE MACH_TYPE_MX31LITE
27
28 /* Temporarily disabled */
29 #if 0
30 #define CONFIG_OF_LIBFDT 1
31 #define CONFIG_FIT 1
32 #define CONFIG_FIT_VERBOSE 1
33 #endif
34
35 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
36 #define CONFIG_SETUP_MEMORY_TAGS 1
37 #define CONFIG_INITRD_TAG 1
38
39 /*
40 * Size of malloc() pool
41 */
42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
43
44 /*
45 * Hardware drivers
46 */
47
48 #define CONFIG_MXC_UART
49 #define CONFIG_MXC_UART_BASE UART1_BASE
50 #define CONFIG_MXC_GPIO
51
52 #define CONFIG_HARD_SPI 1
53 #define CONFIG_MXC_SPI 1
54 #define CONFIG_DEFAULT_SPI_BUS 1
55 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
56
57 /* PMIC Controller */
58 #define CONFIG_POWER
59 #define CONFIG_POWER_SPI
60 #define CONFIG_POWER_FSL
61 #define CONFIG_FSL_PMIC_BUS 1
62 #define CONFIG_FSL_PMIC_CS 0
63 #define CONFIG_FSL_PMIC_CLK 1000000
64 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
65 #define CONFIG_FSL_PMIC_BITLEN 32
66 #define CONFIG_RTC_MC13XXX
67
68 /* allow to overwrite serial and ethaddr */
69 #define CONFIG_ENV_OVERWRITE
70 #define CONFIG_CONS_INDEX 1
71 #define CONFIG_BAUDRATE 115200
72
73 /***********************************************************
74 * Command definition
75 ***********************************************************/
76
77 #include <config_cmd_default.h>
78
79 #define CONFIG_CMD_MII
80 #define CONFIG_CMD_PING
81 #define CONFIG_CMD_SPI
82 #define CONFIG_CMD_DATE
83 #define CONFIG_CMD_NAND
84
85 #define CONFIG_BOOTDELAY 3
86
87 #define CONFIG_NETMASK 255.255.255.0
88 #define CONFIG_IPADDR 192.168.23.168
89 #define CONFIG_SERVERIP 192.168.23.2
90
91 #define CONFIG_EXTRA_ENV_SETTINGS \
92 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
93 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
94 "bootcmd=run bootcmd_net\0" \
95 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
96 "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
97
98
99 #define CONFIG_SMC911X 1
100 #define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
101 #define CONFIG_SMC911X_32_BIT 1
102
103 /*
104 * Miscellaneous configurable options
105 */
106 #define CONFIG_SYS_LONGHELP /* undef to save memory */
107 #define CONFIG_SYS_PROMPT "uboot> "
108 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
109 /* Print Buffer Size */
110 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
111 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
112 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
113
114 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
115 #define CONFIG_SYS_MEMTEST_END 0x10000
116
117 #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
118
119 #define CONFIG_CMDLINE_EDITING 1
120
121 /*-----------------------------------------------------------------------
122 * Physical Memory Map
123 */
124 #define CONFIG_NR_DRAM_BANKS 1
125 #define PHYS_SDRAM_1 CSD0_BASE
126 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
127 #define CONFIG_BOARD_EARLY_INIT_F
128
129 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
130 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
131 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
132 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
133 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
134
135 /*-----------------------------------------------------------------------
136 * FLASH and environment organization
137 */
138 #define CONFIG_SYS_FLASH_BASE CS0_BASE
139 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
140 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
142
143 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
144 #define CONFIG_ENV_IS_IN_FLASH 1
145 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
146 #define CONFIG_ENV_SIZE (64 * 1024)
147
148 /*-----------------------------------------------------------------------
149 * CFI FLASH driver setup
150 */
151 #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
152 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
153 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
154 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
155
156 /* timeout values are in ticks */
157 #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
158 #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
159
160 /*
161 * JFFS2 partitions
162 */
163 #undef CONFIG_CMD_MTDPARTS
164 #define CONFIG_JFFS2_DEV "nor0"
165
166 /*
167 * NAND flash
168 */
169 #define CONFIG_NAND_MXC
170 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
171 #define CONFIG_SYS_MAX_NAND_DEVICE 1
172 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
173 #define CONFIG_MXC_NAND_HWECC
174
175 #endif /* __CONFIG_H */