include/configs/inka4x0.h

   1 /*
   2  * (C) Copyright 2009
   3  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4  *
   5  * (C) Copyright 2003-2005
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU       */
  20 #define CONFIG_INKA4X0          1       /* INKA4x0 board                */
  21 #define CONFIG_DISPLAY_BOARDINFO
  22
  23 /*
  24  * Valid values for CONFIG_SYS_TEXT_BASE are:
  25  * 0xFFE00000   boot low
  26  * 0x00100000   boot from RAM (for testing only)
  27  */
  28 #ifndef CONFIG_SYS_TEXT_BASE
  29 #define CONFIG_SYS_TEXT_BASE    0xFFE00000      /* Standard: boot low */
  30 #endif
  31 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
  32
  33 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  34
  35 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  36
  37 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  38
  39 /*
  40  * Serial console configuration
  41  */
  42 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  43 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  44 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  45
  46 /*
  47  * PCI Mapping:
  48  * 0x40000000 - 0x4fffffff - PCI Memory
  49  * 0x50000000 - 0x50ffffff - PCI IO Space
  50  */
  51 #define CONFIG_PCI              1
  52 #define CONFIG_PCI_PNP          1
  53 #define CONFIG_PCI_SCAN_SHOW    1
  54 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  55
  56 #define CONFIG_PCI_MEM_BUS      0x40000000
  57 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  58 #define CONFIG_PCI_MEM_SIZE     0x10000000
  59
  60 #define CONFIG_PCI_IO_BUS       0x50000000
  61 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  62 #define CONFIG_PCI_IO_SIZE      0x01000000
  63
  64 #define CONFIG_SYS_XLB_PIPELINING       1
  65
  66 /* Partitions */
  67 #define CONFIG_MAC_PARTITION
  68 #define CONFIG_DOS_PARTITION
  69 #define CONFIG_ISO_PARTITION
  70
  71 /*
  72  * BOOTP options
  73  */
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75 #define CONFIG_BOOTP_BOOTPATH
  76 #define CONFIG_BOOTP_GATEWAY
  77 #define CONFIG_BOOTP_HOSTNAME
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #define CONFIG_CMD_DATE
  83 #define CONFIG_CMD_IDE
  84 #define CONFIG_CMD_PCI
  85
  86 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  87
  88 #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)                /* Boot low */
  89 #   define CONFIG_SYS_LOWBOOT           1
  90 #endif
  91
  92 /*
  93  * Autobooting
  94  */
  95 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
  96
  97 #define CONFIG_PREBOOT  "echo;" \
  98         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  99         "echo"
 100
 101 #undef  CONFIG_BOOTARGS
 102
 103 #define CONFIG_IPADDR           192.168.100.2
 104 #define CONFIG_SERVERIP         192.168.100.1
 105 #define CONFIG_NETMASK          255.255.255.0
 106 #define HOSTNAME                inka4x0
 107 #define CONFIG_BOOTFILE         "/tftpboot/inka4x0/uImage"
 108 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 109
 110 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 111         "netdev=eth0\0"                                                 \
 112         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 113                 "nfsroot=${serverip}:${rootpath}\0"                     \
 114         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 115         "addip=setenv bootargs ${bootargs} "                            \
 116                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 117                 ":${hostname}:${netdev}:off panic=1\0"                  \
 118         "addcons=setenv bootargs ${bootargs} "                          \
 119                 "console=ttyS0,${baudrate}\0"                           \
 120         "flash_nfs=run nfsargs addip addcons;"                          \
 121                 "bootm ${kernel_addr}\0"                                \
 122         "net_nfs=tftp 200000 ${bootfile};"                              \
 123                 "run nfsargs addip addcons;bootm\0"                     \
 124         "enable_disp=mw.l 100000 04000000 1;"                           \
 125                 "cp.l 100000 f0000b20 1;"                               \
 126                 "cp.l 100000 f0000b28 1\0"                              \
 127         "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 128         "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 129                 "run ideargs addip addcons enable_disp;bootm\0"         \
 130         "brightness=255\0"                                              \
 131         ""
 132
 133 #define CONFIG_BOOTCOMMAND      "run ide_boot"
 134
 135 /*
 136  * IPB Bus clocking configuration.
 137  */
 138 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 139
 140 /*
 141  * Flash configuration
 142  */
 143 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 144 #define CONFIG_FLASH_CFI_DRIVER 1
 145 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 146 #define CONFIG_SYS_FLASH_SIZE           0x00200000
 147 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 148 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 149 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 151
 152 /*
 153  * Environment settings
 154  */
 155 #define CONFIG_ENV_IS_IN_FLASH  1
 156 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 157 #define CONFIG_ENV_SIZE         0x2000
 158 #define CONFIG_ENV_SECT_SIZE    0x2000
 159 #define CONFIG_ENV_OVERWRITE    1
 160 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 161
 162 /*
 163  * Memory map
 164  */
 165 #define CONFIG_SYS_MBAR         0xF0000000
 166 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 167 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 168
 169 /*
 170  * SDRAM controller configuration
 171  */
 172 #undef CONFIG_SDR_MT48LC16M16A2
 173 #undef CONFIG_DDR_MT46V16M16
 174 #undef CONFIG_DDR_MT46V32M16
 175 #undef CONFIG_DDR_HYB25D512160BF
 176 #define CONFIG_DDR_K4H511638C
 177
 178 /* Use ON-Chip SRAM until RAM will be available */
 179 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 180
 181 /* preserve space for the post_word at end of on-chip SRAM */
 182 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 183
 184 #ifdef CONFIG_POST
 185 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 186 #else
 187 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 188 #endif
 189
 190 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 191 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 192
 193 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 194 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 195 #   define CONFIG_SYS_RAMBOOT           1
 196 #endif
 197
 198 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 199 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 200 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 201
 202 /*
 203  * Ethernet configuration
 204  */
 205 #define CONFIG_MPC5xxx_FEC      1
 206 #define CONFIG_MPC5xxx_FEC_MII100
 207 /*
 208  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 209  */
 210 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 211 #define CONFIG_PHY_ADDR         0x00
 212 #define CONFIG_MII
 213
 214 /*
 215  * GPIO configuration
 216  *
 217  * use CS1 as gpio_wkup_6 output
 218  *      Bit 0 (mask: 0x80000000): 0
 219  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 220  *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 221  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 222  *            EEPROM
 223  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 224  * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 225  * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 226  * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 227  */
 228 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 229
 230 /*
 231  * RTC configuration
 232  */
 233 #define CONFIG_RTC_RTC4543      1       /* use external RTC */
 234
 235 /*
 236  * Software (bit-bang) three wire serial configuration
 237  *
 238  * Note that we need the ifdefs because otherwise compilation of
 239  * mkimage.c fails.
 240  */
 241 #define CONFIG_SOFT_TWS         1
 242
 243 #ifdef TWS_IMPLEMENTATION
 244 #include <mpc5xxx.h>
 245 #include <asm/io.h>
 246
 247 #define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 248 #define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 249 #define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 250 #define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 251
 252 static inline void tws_ce(unsigned bit)
 253 {
 254         struct mpc5xxx_wu_gpio *wu_gpio =
 255                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 256         if (bit)
 257                 setbits_8(&wu_gpio->dvo, TWS_CE);
 258         else
 259                 clrbits_8(&wu_gpio->dvo, TWS_CE);
 260 }
 261
 262 static inline void tws_wr(unsigned bit)
 263 {
 264         struct mpc5xxx_wu_gpio *wu_gpio =
 265                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 266         if (bit)
 267                 setbits_8(&wu_gpio->dvo, TWS_WR);
 268         else
 269                 clrbits_8(&wu_gpio->dvo, TWS_WR);
 270 }
 271
 272 static inline void tws_clk(unsigned bit)
 273 {
 274         struct mpc5xxx_gpio *gpio =
 275                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 276         if (bit)
 277                 setbits_8(&gpio->sint_dvo, TWS_CLK);
 278         else
 279                 clrbits_8(&gpio->sint_dvo, TWS_CLK);
 280 }
 281
 282 static inline void tws_data(unsigned bit)
 283 {
 284         struct mpc5xxx_gpio *gpio =
 285                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 286         if (bit)
 287                 setbits_8(&gpio->sint_dvo, TWS_DATA);
 288         else
 289                 clrbits_8(&gpio->sint_dvo, TWS_DATA);
 290 }
 291
 292 static inline unsigned tws_data_read(void)
 293 {
 294         struct mpc5xxx_gpio *gpio =
 295                         (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 296         return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 297 }
 298
 299 static inline void tws_data_config_output(unsigned output)
 300 {
 301         struct mpc5xxx_gpio *gpio =
 302                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 303         if (output)
 304                 setbits_8(&gpio->sint_ddr, TWS_DATA);
 305         else
 306                 clrbits_8(&gpio->sint_ddr, TWS_DATA);
 307 }
 308 #endif /* TWS_IMPLEMENTATION */
 309
 310 /*
 311  * Miscellaneous configurable options
 312  */
 313 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 314 #if defined(CONFIG_CMD_KGDB)
 315 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 316 #else
 317 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 318 #endif
 319 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 320 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 321 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 322
 323 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 324 #if defined(CONFIG_CMD_KGDB)
 325 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 326 #endif
 327
 328 /* Enable an alternate, more extensive memory test */
 329 #define CONFIG_SYS_ALT_MEMTEST
 330
 331 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 332 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 333
 334 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 335
 336 /*
 337  * Various low-level settings
 338  */
 339 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 340 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 341
 342 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 343 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 344 #define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 345 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 346 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 347
 348 /* 32Mbit SRAM @0x30000000 */
 349 #define CONFIG_SYS_CS1_START            0x30000000
 350 #define CONFIG_SYS_CS1_SIZE             0x00400000
 351 #define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 352
 353 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 354 #define CONFIG_SYS_CS2_START            0x80000000
 355 #define CONFIG_SYS_CS2_SIZE             0x0001000
 356 #define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 357
 358 /* GPIO in @0x30400000 */
 359 #define CONFIG_SYS_CS3_START            0x30400000
 360 #define CONFIG_SYS_CS3_SIZE             0x00100000
 361 #define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 362
 363 #define CONFIG_SYS_CS_BURST             0x00000000
 364 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 365
 366 /*-----------------------------------------------------------------------
 367  * USB stuff
 368  *-----------------------------------------------------------------------
 369  */
 370 #define CONFIG_USB_OHCI
 371 #define CONFIG_USB_CLOCK        0x00015555
 372 #define CONFIG_USB_CONFIG       0x00001000
 373 #define CONFIG_USB_STORAGE
 374
 375 /*-----------------------------------------------------------------------
 376  * IDE/ATA stuff Supports IDE harddisk
 377  *-----------------------------------------------------------------------
 378  */
 379
 380 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 381
 382 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 383 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 384
 385 #define CONFIG_IDE_PREINIT
 386
 387 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 388 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 389
 390 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 391 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 392 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 393 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 394 #define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 395 #define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 396
 397 #define CONFIG_ATAPI            1
 398
 399 #define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 400
 401 #endif /* __CONFIG_H */