include/configs/inka4x0.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  33 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU)      */
  34 #define CONFIG_INKA4X0          1       /* INKA4x0 board                        */
  35
  36 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz         */
  37
  38 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
  39 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
  40
  41 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  42
  43 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  44
  45 /*
  46  * Serial console configuration
  47  */
  48 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  49 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  50 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  51
  52 /*
  53  * PCI Mapping:
  54  * 0x40000000 - 0x4fffffff - PCI Memory
  55  * 0x50000000 - 0x50ffffff - PCI IO Space
  56  */
  57 #define CONFIG_PCI              1
  58 #define CONFIG_PCI_PNP          1
  59 #define CONFIG_PCI_SCAN_SHOW    1
  60 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  61
  62 #define CONFIG_PCI_MEM_BUS      0x40000000
  63 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  64 #define CONFIG_PCI_MEM_SIZE     0x10000000
  65
  66 #define CONFIG_PCI_IO_BUS       0x50000000
  67 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  68 #define CONFIG_PCI_IO_SIZE      0x01000000
  69
  70 #define CFG_XLB_PIPELINING      1
  71
  72 /* Partitions */
  73 #define CONFIG_MAC_PARTITION
  74 #define CONFIG_DOS_PARTITION
  75 #define CONFIG_ISO_PARTITION
  76
  77
  78 /*
  79  * BOOTP options
  80  */
  81 #define CONFIG_BOOTP_BOOTFILESIZE
  82 #define CONFIG_BOOTP_BOOTPATH
  83 #define CONFIG_BOOTP_GATEWAY
  84 #define CONFIG_BOOTP_HOSTNAME
  85
  86
  87 /*
  88  * Command line configuration.
  89  */
  90 #include <config_cmd_default.h>
  91
  92 #define CONFIG_CMD_DHCP
  93 #define CONFIG_CMD_EXT2
  94 #define CONFIG_CMD_FAT
  95 #define CONFIG_CMD_IDE
  96 #define CONFIG_CMD_NFS
  97 #define CONFIG_CMD_PCI
  98 #define CONFIG_CMD_SNTP
  99 #define CONFIG_CMD_USB
 100
 101
 102 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
 103
 104 #if (TEXT_BASE == 0xFFE00000)           /* Boot low */
 105 #   define CFG_LOWBOOT          1
 106 #endif
 107
 108 /*
 109  * Autobooting
 110  */
 111 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 112
 113 #define CONFIG_PREBOOT  "echo;" \
 114         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 115         "echo"
 116
 117 #undef  CONFIG_BOOTARGS
 118
 119 #define CONFIG_ETHADDR          00:a0:a4:03:00:00
 120 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 121
 122 #define CONFIG_IPADDR           192.168.100.2
 123 #define CONFIG_SERVERIP         192.168.100.1
 124 #define CONFIG_NETMASK          255.255.255.0
 125 #define HOSTNAME                inka4x0
 126 #define CONFIG_BOOTFILE         /tftpboot/inka4x0/uImage
 127 #define CONFIG_ROOTPATH         /opt/eldk/ppc_6xx
 128
 129 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 130         "netdev=eth0\0"                                                 \
 131         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 132                 "nfsroot=${serverip}:${rootpath}\0"                     \
 133         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 134         "addip=setenv bootargs ${bootargs} "                            \
 135                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 136                 ":${hostname}:${netdev}:off panic=1\0"                  \
 137         "addcons=setenv bootargs ${bootargs} "                          \
 138                 "console=ttyS0,${baudrate}\0"                           \
 139         "flash_nfs=run nfsargs addip addcons;"                          \
 140                 "bootm ${kernel_addr}\0"                                \
 141         "net_nfs=tftp 200000 ${bootfile};"                              \
 142                 "run nfsargs addip addcons;bootm\0"                     \
 143         "enable_disp=mw.l 100000 04000000 1;"                           \
 144                 "cp.l 100000 f0000b20 1;"                               \
 145                 "cp.l 100000 f0000b28 1\0"                              \
 146         "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 147         "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 148                 "run ideargs addip addcons enable_disp;bootm\0"         \
 149         "brightness=255\0"                                              \
 150         ""
 151
 152 #define CONFIG_BOOTCOMMAND      "run ide_boot"
 153
 154 /*
 155  * IPB Bus clocking configuration.
 156  */
 157 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 158
 159 /*
 160  * Flash configuration
 161  */
 162 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 163 #define CONFIG_FLASH_CFI_DRIVER 1
 164 #define CFG_FLASH_BASE          0xffe00000
 165 #define CFG_FLASH_SIZE          0x00200000
 166 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks */
 167 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 168 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 169 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
 170
 171 /*
 172  * Environment settings
 173  */
 174 #define CONFIG_ENV_IS_IN_FLASH  1
 175 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x4000)
 176 #define CFG_ENV_SIZE            0x2000
 177 #define CFG_ENV_SECT_SIZE       0x2000
 178 #define CONFIG_ENV_OVERWRITE    1
 179 #define CFG_USE_PPCENV                  /* Environment embedded in sect .ppcenv */
 180
 181 /*
 182  * Memory map
 183  */
 184 #define CFG_MBAR                0xF0000000
 185 #define CFG_SDRAM_BASE          0x00000000
 186 #define CFG_DEFAULT_MBAR        0x80000000
 187
 188 /*
 189  * SDRAM controller configuration
 190  */
 191 #undef CONFIG_SDR_MT48LC16M16A2
 192 #undef CONFIG_DDR_MT46V16M16
 193 #undef CONFIG_DDR_MT46V32M16
 194 #undef CONFIG_DDR_HYB25D512160BF
 195 #define CONFIG_DDR_K4H511638C
 196
 197 /* Use ON-Chip SRAM until RAM will be available */
 198 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 199 #ifdef CONFIG_POST
 200 /* preserve space for the post_word at end of on-chip SRAM */
 201 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 202 #else
 203 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 204 #endif
 205
 206
 207 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 208 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 209 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 210
 211 #define CFG_MONITOR_BASE    TEXT_BASE
 212 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 213 #   define CFG_RAMBOOT          1
 214 #endif
 215
 216 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 217 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 218 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 219
 220 /*
 221  * Ethernet configuration
 222  */
 223 #define CONFIG_MPC5xxx_FEC      1
 224 /*
 225  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 226  */
 227 /* #define CONFIG_FEC_10MBIT 1 */
 228 #define CONFIG_PHY_ADDR         0x00
 229 #define CONFIG_MII
 230
 231 /*
 232  * GPIO configuration
 233  *
 234  * use CS1 as gpio_wkup_6 output
 235  *      Bit 0 (mask: 0x80000000): 0
 236  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 237  *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 238  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 239  *            EEPROM
 240  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 241  * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
 242  *      011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
 243  */
 244 #define CFG_GPS_PORT_CONFIG     0x01001004
 245
 246 /*
 247  * RTC configuration
 248  */
 249 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 250
 251 /*
 252  * Miscellaneous configurable options
 253  */
 254 #define CFG_LONGHELP                    /* undef to save memory     */
 255 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 256 #if defined(CONFIG_CMD_KGDB)
 257 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 258 #else
 259 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 260 #endif
 261 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 262 #define CFG_MAXARGS             16      /* max number of command args   */
 263 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 264
 265 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs                     */
 266 #if defined(CONFIG_CMD_KGDB)
 267 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
 268 #endif
 269
 270 /* Enable an alternate, more extensive memory test */
 271 #define CFG_ALT_MEMTEST
 272
 273 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 274 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 275
 276 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 277
 278 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 279
 280 /*
 281  * Enable loopw command.
 282  */
 283 #define CONFIG_LOOPW
 284
 285 /*
 286  * Various low-level settings
 287  */
 288 #if defined(CONFIG_MPC5200)
 289 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 290 #define CFG_HID0_FINAL          HID0_ICE
 291 #else
 292 #define CFG_HID0_INIT           0
 293 #define CFG_HID0_FINAL          0
 294 #endif
 295
 296 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 297 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 298 #define CFG_BOOTCS_CFG          0x00087800 /* for pci_clk  = 66 MHz */
 299 #define CFG_CS0_START           CFG_FLASH_BASE
 300 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 301
 302 /* 32Mbit SRAM @0x30000000 */
 303 #define CFG_CS1_START           0x30000000
 304 #define CFG_CS1_SIZE            0x00400000
 305 #define CFG_CS1_CFG             0x31800 /* for pci_clk = 33 MHz */
 306
 307 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 308 #define CFG_CS2_START           0x80000000
 309 #define CFG_CS2_SIZE            0x0001000
 310 #define CFG_CS2_CFG             0x21800  /* for pci_clk = 33 MHz */
 311
 312 /* GPIO in @0x30400000 */
 313 #define CFG_CS3_START           0x30400000
 314 #define CFG_CS3_SIZE            0x00100000
 315 #define CFG_CS3_CFG             0x31800 /* for pci_clk = 33 MHz */
 316
 317 #define CFG_CS_BURST            0x00000000
 318 #define CFG_CS_DEADCYCLE        0x33333333
 319
 320 /*-----------------------------------------------------------------------
 321  * USB stuff
 322  *-----------------------------------------------------------------------
 323  */
 324 #define CONFIG_USB_OHCI
 325 #define CONFIG_USB_CLOCK        0x00015555
 326 #define CONFIG_USB_CONFIG       0x00001000
 327 #define CONFIG_USB_STORAGE
 328
 329 /*-----------------------------------------------------------------------
 330  * IDE/ATA stuff Supports IDE harddisk
 331  *-----------------------------------------------------------------------
 332  */
 333
 334 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 335
 336 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 337 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 338
 339 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 340 #define CONFIG_IDE_PREINIT
 341
 342 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 343 #define CFG_IDE_MAXDEVICE       2       /* max. 1 drive per IDE bus     */
 344
 345 #define CFG_ATA_IDE0_OFFSET     0x0000
 346 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 347 #define CFG_ATA_DATA_OFFSET     0x0060  /* Offset for data I/O          */
 348 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 349 #define CFG_ATA_ALT_OFFSET      0x005C  /* Offset for alternate registers */
 350 #define CFG_ATA_STRIDE          4       /* Interval between registers   */
 351
 352 #define CONFIG_ATAPI            1
 353
 354 #define CFG_BRIGHTNESS          0xFF    /* LCD Default Brightness (255 = off) */
 355
 356 #endif /* __CONFIG_H */