include/configs/inka4x0.h

   1 /*
   2  * (C) Copyright 2009
   3  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4  *
   5  * (C) Copyright 2003-2005
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU       */
  20 #define CONFIG_INKA4X0          1       /* INKA4x0 board                */
  21
  22 /*
  23  * Valid values for CONFIG_SYS_TEXT_BASE are:
  24  * 0xFFE00000   boot low
  25  * 0x00100000   boot from RAM (for testing only)
  26  */
  27 #ifndef CONFIG_SYS_TEXT_BASE
  28 #define CONFIG_SYS_TEXT_BASE    0xFFE00000      /* Standard: boot low */
  29 #endif
  30 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
  31
  32 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  33
  34 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  35
  36 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  37
  38 /*
  39  * Serial console configuration
  40  */
  41 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  42 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  43
  44 /*
  45  * PCI Mapping:
  46  * 0x40000000 - 0x4fffffff - PCI Memory
  47  * 0x50000000 - 0x50ffffff - PCI IO Space
  48  */
  49 #define CONFIG_PCI_SCAN_SHOW    1
  50 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  51
  52 #define CONFIG_PCI_MEM_BUS      0x40000000
  53 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  54 #define CONFIG_PCI_MEM_SIZE     0x10000000
  55
  56 #define CONFIG_PCI_IO_BUS       0x50000000
  57 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  58 #define CONFIG_PCI_IO_SIZE      0x01000000
  59
  60 #define CONFIG_SYS_XLB_PIPELINING       1
  61
  62 /* Partitions */
  63
  64 /*
  65  * BOOTP options
  66  */
  67 #define CONFIG_BOOTP_BOOTFILESIZE
  68 #define CONFIG_BOOTP_BOOTPATH
  69 #define CONFIG_BOOTP_GATEWAY
  70 #define CONFIG_BOOTP_HOSTNAME
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #define CONFIG_CMD_DATE
  76 #define CONFIG_CMD_IDE
  77 #define CONFIG_CMD_PCI
  78
  79 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  80
  81 #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)                /* Boot low */
  82 #   define CONFIG_SYS_LOWBOOT           1
  83 #endif
  84
  85 /*
  86  * Autobooting
  87  */
  88
  89 #define CONFIG_PREBOOT  "echo;" \
  90         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  91         "echo"
  92
  93 #undef  CONFIG_BOOTARGS
  94
  95 #define CONFIG_IPADDR           192.168.100.2
  96 #define CONFIG_SERVERIP         192.168.100.1
  97 #define CONFIG_NETMASK          255.255.255.0
  98 #define HOSTNAME                inka4x0
  99 #define CONFIG_BOOTFILE         "/tftpboot/inka4x0/uImage"
 100 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 101
 102 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 103         "netdev=eth0\0"                                                 \
 104         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 105                 "nfsroot=${serverip}:${rootpath}\0"                     \
 106         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 107         "addip=setenv bootargs ${bootargs} "                            \
 108                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 109                 ":${hostname}:${netdev}:off panic=1\0"                  \
 110         "addcons=setenv bootargs ${bootargs} "                          \
 111                 "console=ttyS0,${baudrate}\0"                           \
 112         "flash_nfs=run nfsargs addip addcons;"                          \
 113                 "bootm ${kernel_addr}\0"                                \
 114         "net_nfs=tftp 200000 ${bootfile};"                              \
 115                 "run nfsargs addip addcons;bootm\0"                     \
 116         "enable_disp=mw.l 100000 04000000 1;"                           \
 117                 "cp.l 100000 f0000b20 1;"                               \
 118                 "cp.l 100000 f0000b28 1\0"                              \
 119         "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 120         "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 121                 "run ideargs addip addcons enable_disp;bootm\0"         \
 122         "brightness=255\0"                                              \
 123         ""
 124
 125 #define CONFIG_BOOTCOMMAND      "run ide_boot"
 126
 127 /*
 128  * IPB Bus clocking configuration.
 129  */
 130 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 131
 132 /*
 133  * Flash configuration
 134  */
 135 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 136 #define CONFIG_FLASH_CFI_DRIVER 1
 137 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 138 #define CONFIG_SYS_FLASH_SIZE           0x00200000
 139 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 140 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 141 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 143
 144 /*
 145  * Environment settings
 146  */
 147 #define CONFIG_ENV_IS_IN_FLASH  1
 148 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 149 #define CONFIG_ENV_SIZE         0x2000
 150 #define CONFIG_ENV_SECT_SIZE    0x2000
 151 #define CONFIG_ENV_OVERWRITE    1
 152 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 153
 154 /*
 155  * Memory map
 156  */
 157 #define CONFIG_SYS_MBAR         0xF0000000
 158 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 159 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 160
 161 /*
 162  * SDRAM controller configuration
 163  */
 164 #undef CONFIG_SDR_MT48LC16M16A2
 165 #undef CONFIG_DDR_MT46V16M16
 166 #undef CONFIG_DDR_MT46V32M16
 167 #undef CONFIG_DDR_HYB25D512160BF
 168 #define CONFIG_DDR_K4H511638C
 169
 170 /* Use ON-Chip SRAM until RAM will be available */
 171 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 172
 173 /* preserve space for the post_word at end of on-chip SRAM */
 174 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 175
 176 #ifdef CONFIG_POST
 177 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 178 #else
 179 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 180 #endif
 181
 182 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 183 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 184
 185 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 186 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 187 #   define CONFIG_SYS_RAMBOOT           1
 188 #endif
 189
 190 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 191 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 192 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 193
 194 /*
 195  * Ethernet configuration
 196  */
 197 #define CONFIG_MPC5xxx_FEC      1
 198 #define CONFIG_MPC5xxx_FEC_MII100
 199 /*
 200  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 201  */
 202 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 203 #define CONFIG_PHY_ADDR         0x00
 204 #define CONFIG_MII
 205
 206 /*
 207  * GPIO configuration
 208  *
 209  * use CS1 as gpio_wkup_6 output
 210  *      Bit 0 (mask: 0x80000000): 0
 211  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 212  *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 213  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 214  *            EEPROM
 215  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 216  * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 217  * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 218  * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 219  */
 220 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 221
 222 /*
 223  * RTC configuration
 224  */
 225 #define CONFIG_RTC_RTC4543      1       /* use external RTC */
 226
 227 /*
 228  * Software (bit-bang) three wire serial configuration
 229  *
 230  * Note that we need the ifdefs because otherwise compilation of
 231  * mkimage.c fails.
 232  */
 233 #define CONFIG_SOFT_TWS         1
 234
 235 #ifdef TWS_IMPLEMENTATION
 236 #include <mpc5xxx.h>
 237 #include <asm/io.h>
 238
 239 #define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 240 #define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 241 #define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 242 #define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 243
 244 static inline void tws_ce(unsigned bit)
 245 {
 246         struct mpc5xxx_wu_gpio *wu_gpio =
 247                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 248         if (bit)
 249                 setbits_8(&wu_gpio->dvo, TWS_CE);
 250         else
 251                 clrbits_8(&wu_gpio->dvo, TWS_CE);
 252 }
 253
 254 static inline void tws_wr(unsigned bit)
 255 {
 256         struct mpc5xxx_wu_gpio *wu_gpio =
 257                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 258         if (bit)
 259                 setbits_8(&wu_gpio->dvo, TWS_WR);
 260         else
 261                 clrbits_8(&wu_gpio->dvo, TWS_WR);
 262 }
 263
 264 static inline void tws_clk(unsigned bit)
 265 {
 266         struct mpc5xxx_gpio *gpio =
 267                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 268         if (bit)
 269                 setbits_8(&gpio->sint_dvo, TWS_CLK);
 270         else
 271                 clrbits_8(&gpio->sint_dvo, TWS_CLK);
 272 }
 273
 274 static inline void tws_data(unsigned bit)
 275 {
 276         struct mpc5xxx_gpio *gpio =
 277                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 278         if (bit)
 279                 setbits_8(&gpio->sint_dvo, TWS_DATA);
 280         else
 281                 clrbits_8(&gpio->sint_dvo, TWS_DATA);
 282 }
 283
 284 static inline unsigned tws_data_read(void)
 285 {
 286         struct mpc5xxx_gpio *gpio =
 287                         (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 288         return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 289 }
 290
 291 static inline void tws_data_config_output(unsigned output)
 292 {
 293         struct mpc5xxx_gpio *gpio =
 294                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 295         if (output)
 296                 setbits_8(&gpio->sint_ddr, TWS_DATA);
 297         else
 298                 clrbits_8(&gpio->sint_ddr, TWS_DATA);
 299 }
 300 #endif /* TWS_IMPLEMENTATION */
 301
 302 /*
 303  * Miscellaneous configurable options
 304  */
 305 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 306 #if defined(CONFIG_CMD_KGDB)
 307 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 308 #else
 309 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 310 #endif
 311 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 312 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 313 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 314
 315 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 316 #if defined(CONFIG_CMD_KGDB)
 317 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 318 #endif
 319
 320 /* Enable an alternate, more extensive memory test */
 321 #define CONFIG_SYS_ALT_MEMTEST
 322
 323 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 324 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 325
 326 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 327
 328 /*
 329  * Various low-level settings
 330  */
 331 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 332 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 333
 334 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 335 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 336 #define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 337 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 338 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 339
 340 /* 32Mbit SRAM @0x30000000 */
 341 #define CONFIG_SYS_CS1_START            0x30000000
 342 #define CONFIG_SYS_CS1_SIZE             0x00400000
 343 #define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 344
 345 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 346 #define CONFIG_SYS_CS2_START            0x80000000
 347 #define CONFIG_SYS_CS2_SIZE             0x0001000
 348 #define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 349
 350 /* GPIO in @0x30400000 */
 351 #define CONFIG_SYS_CS3_START            0x30400000
 352 #define CONFIG_SYS_CS3_SIZE             0x00100000
 353 #define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 354
 355 #define CONFIG_SYS_CS_BURST             0x00000000
 356 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 357
 358 /*-----------------------------------------------------------------------
 359  * USB stuff
 360  *-----------------------------------------------------------------------
 361  */
 362 #define CONFIG_USB_OHCI
 363 #define CONFIG_USB_CLOCK        0x00015555
 364 #define CONFIG_USB_CONFIG       0x00001000
 365
 366 /*-----------------------------------------------------------------------
 367  * IDE/ATA stuff Supports IDE harddisk
 368  *-----------------------------------------------------------------------
 369  */
 370
 371 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 372
 373 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 374 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 375
 376 #define CONFIG_IDE_PREINIT
 377
 378 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 379 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 380
 381 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 382 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 383 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 384 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 385 #define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 386 #define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 387
 388 #define CONFIG_ATAPI            1
 389
 390 #define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 391
 392 #endif /* __CONFIG_H */