include/configs/integratorap.h

   1 /*
   2  * (C) Copyright 2003
   3  * Texas Instruments.
   4  * Kshitij Gupta <kshitij@ti.com>
   5  * Configuation settings for the TI OMAP Innovator board.
   6  *
   7  * (C) Copyright 2004
   8  * ARM Ltd.
   9  * Philippe Robin, <philippe.robin@arm.com>
  10  * Configuration for Integrator AP board.
  11  *.
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 #define CONFIG_INTEGRATOR
  35 #define CONFIG_ARCH_INTEGRATOR
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40 #define CONFIG_SYS_TEXT_BASE            0x01000000
  41 #define CONFIG_SYS_MEMTEST_START        0x100000
  42 #define CONFIG_SYS_MEMTEST_END          0x10000000
  43 #define CONFIG_SYS_HZ                   1000
  44 #define CONFIG_SYS_HZ_CLOCK             24000000        /* Timer 1 is clocked at 24Mhz */
  45 #define CONFIG_SYS_TIMERBASE            0x13000100      /* Timer1                      */
  46
  47 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs  */
  48 #define CONFIG_SETUP_MEMORY_TAGS        1
  49 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r during start up */
  50
  51 #define CONFIG_SKIP_LOWLEVEL_INIT
  52 #define CONFIG_CM_INIT          1
  53 #define CONFIG_CM_REMAP         1
  54 #define CONFIG_CM_SPD_DETECT
  55
  56 /*
  57  * Size of malloc() pool
  58  */
  59 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 128*1024)
  60
  61 /*
  62  * PL010 Configuration
  63  */
  64 #define CONFIG_PL010_SERIAL
  65 #define CONFIG_CONS_INDEX       0
  66 #define CONFIG_BAUDRATE         38400
  67 #define CONFIG_PL01x_PORTS      { (void *) (CONFIG_SYS_SERIAL0), (void *) (CONFIG_SYS_SERIAL1) }
  68 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  69 #define CONFIG_SYS_SERIAL0              0x16000000
  70 #define CONFIG_SYS_SERIAL1              0x17000000
  71
  72
  73 /*
  74  * BOOTP options
  75  */
  76 #define CONFIG_BOOTP_BOOTFILESIZE
  77 #define CONFIG_BOOTP_BOOTPATH
  78 #define CONFIG_BOOTP_GATEWAY
  79 #define CONFIG_BOOTP_HOSTNAME
  80
  81
  82 /*
  83  * Command line configuration.
  84  */
  85
  86
  87 #define CONFIG_CMD_IMI
  88 #define CONFIG_CMD_BDI
  89 #define CONFIG_CMD_BOOTD
  90 #define CONFIG_CMD_MEMORY
  91 #define CONFIG_CMD_FLASH
  92 #define CONFIG_CMD_IMLS
  93 #define CONFIG_CMD_LOADB
  94 #define CONFIG_CMD_LOADS
  95
  96
  97 #define CONFIG_BOOTDELAY        2
  98 #define CONFIG_BOOTARGS         "root=/dev/mtdblock0 console=ttyAM0 console=tty"
  99 #define CONFIG_BOOTCOMMAND      ""
 100
 101 /*
 102  * Miscellaneous configurable options
 103  */
 104 #define CONFIG_SYS_LONGHELP     /* undef to save memory     */
 105 #define CONFIG_SYS_HUSH_PARSER
 106 #define CONFIG_SYS_PROMPT       "Integrator-AP # "      /* Monitor Command Prompt   */
 107 #define CONFIG_SYS_PROMPT_HUSH_PS2      "# "
 108 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size  */
 109 /* Print Buffer Size */
 110 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 111 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 112 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 113
 114 #define CONFIG_SYS_LOAD_ADDR    0x7fc0  /* default load address */
 115
 116 /*-----------------------------------------------------------------------
 117  * Stack sizes
 118  *
 119  * The stack sizes are set up in start.S using the settings below
 120  */
 121 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 122 #ifdef CONFIG_USE_IRQ
 123 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 124 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 125 #endif
 126
 127 /*-----------------------------------------------------------------------
 128  * Physical Memory Map
 129  */
 130 #define CONFIG_NR_DRAM_BANKS    1       /* we have 1 bank of DRAM */
 131 #define PHYS_SDRAM_1            0x00000000      /* SDRAM Bank #1 */
 132 #define PHYS_SDRAM_1_SIZE       0x02000000      /* 32 MB */
 133 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM_1
 134 #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
 135 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
 136                                     CONFIG_SYS_INIT_RAM_SIZE - \
 137                                     GENERATED_GBL_DATA_SIZE)
 138 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
 139
 140 #define CONFIG_SYS_FLASH_BASE   0x24000000
 141
 142 /*-----------------------------------------------------------------------
 143  * FLASH and environment organization
 144  */
 145 #define CONFIG_SYS_FLASH_CFI            1
 146 #define CONFIG_FLASH_CFI_DRIVER         1
 147 #define CONFIG_ENV_IS_NOWHERE
 148 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* max number of memory banks */
 149 /* timeout values are in ticks */
 150 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ)       /* Timeout for Flash Erase */
 151 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ)       /* Timeout for Flash Write */
 152 #define CONFIG_SYS_MAX_FLASH_SECT       128
 153 #define CONFIG_ENV_SIZE                 32768
 154
 155
 156 /*-----------------------------------------------------------------------
 157  * PCI definitions
 158  */
 159
 160 #ifdef CONFIG_PCI                       /* pci support  */
 161 #undef CONFIG_PCI_PNP
 162 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 163 #define DEBUG
 164
 165 #define CONFIG_EEPRO100
 166 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
 167
 168 #define INTEGRATOR_BOOT_ROM_BASE        0x20000000
 169 #define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
 170
 171 /* PCI Base area */
 172 #define INTEGRATOR_PCI_BASE             0x40000000
 173 #define INTEGRATOR_PCI_SIZE             0x3FFFFFFF
 174
 175 /* memory map as seen by the CPU on the local bus */
 176 #define CPU_PCI_IO_ADRS         0x60000000      /* PCI I/O space base */
 177 #define CPU_PCI_IO_SIZE         0x10000
 178
 179 #define CPU_PCI_CNFG_ADRS       0x61000000      /* PCI config space */
 180 #define CPU_PCI_CNFG_SIZE       0x1000000
 181
 182 #define PCI_MEM_BASE            0x40000000   /* 512M to xxx */
 183 /*  unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
 184 #define INTEGRATOR_PCI_IO_BASE  0x60000000   /* 16M to xxx */
 185 /*  unused (128-16)M from B1000000-B7FFFFFF */
 186 #define PCI_CONFIG_BASE         0x61000000   /* 16M to xxx */
 187 /*  unused ((128-16)M - 64K) from XXX */
 188
 189 #define PCI_V3_BASE             0x62000000
 190
 191 /* V3 PCI bridge controller */
 192 #define V3_BASE                 0x62000000    /* V360EPC registers */
 193
 194 #define PCI_ENET0_IOADDR        (CPU_PCI_IO_ADRS)
 195 #define PCI_ENET0_MEMADDR       (PCI_MEM_BASE)
 196
 197
 198 #define V3_PCI_VENDOR           0x00000000
 199 #define V3_PCI_DEVICE           0x00000002
 200 #define V3_PCI_CMD              0x00000004
 201 #define V3_PCI_STAT             0x00000006
 202 #define V3_PCI_CC_REV           0x00000008
 203 #define V3_PCI_HDR_CF           0x0000000C
 204 #define V3_PCI_IO_BASE          0x00000010
 205 #define V3_PCI_BASE0            0x00000014
 206 #define V3_PCI_BASE1            0x00000018
 207 #define V3_PCI_SUB_VENDOR       0x0000002C
 208 #define V3_PCI_SUB_ID           0x0000002E
 209 #define V3_PCI_ROM              0x00000030
 210 #define V3_PCI_BPARAM           0x0000003C
 211 #define V3_PCI_MAP0             0x00000040
 212 #define V3_PCI_MAP1             0x00000044
 213 #define V3_PCI_INT_STAT         0x00000048
 214 #define V3_PCI_INT_CFG          0x0000004C
 215 #define V3_LB_BASE0             0x00000054
 216 #define V3_LB_BASE1             0x00000058
 217 #define V3_LB_MAP0              0x0000005E
 218 #define V3_LB_MAP1              0x00000062
 219 #define V3_LB_BASE2             0x00000064
 220 #define V3_LB_MAP2              0x00000066
 221 #define V3_LB_SIZE              0x00000068
 222 #define V3_LB_IO_BASE           0x0000006E
 223 #define V3_FIFO_CFG             0x00000070
 224 #define V3_FIFO_PRIORITY        0x00000072
 225 #define V3_FIFO_STAT            0x00000074
 226 #define V3_LB_ISTAT             0x00000076
 227 #define V3_LB_IMASK             0x00000077
 228 #define V3_SYSTEM               0x00000078
 229 #define V3_LB_CFG               0x0000007A
 230 #define V3_PCI_CFG              0x0000007C
 231 #define V3_DMA_PCI_ADR0         0x00000080
 232 #define V3_DMA_PCI_ADR1         0x00000090
 233 #define V3_DMA_LOCAL_ADR0       0x00000084
 234 #define V3_DMA_LOCAL_ADR1       0x00000094
 235 #define V3_DMA_LENGTH0          0x00000088
 236 #define V3_DMA_LENGTH1          0x00000098
 237 #define V3_DMA_CSR0             0x0000008B
 238 #define V3_DMA_CSR1             0x0000009B
 239 #define V3_DMA_CTLB_ADR0        0x0000008C
 240 #define V3_DMA_CTLB_ADR1        0x0000009C
 241 #define V3_DMA_DELAY            0x000000E0
 242 #define V3_MAIL_DATA            0x000000C0
 243 #define V3_PCI_MAIL_IEWR        0x000000D0
 244 #define V3_PCI_MAIL_IERD        0x000000D2
 245 #define V3_LB_MAIL_IEWR         0x000000D4
 246 #define V3_LB_MAIL_IERD         0x000000D6
 247 #define V3_MAIL_WR_STAT         0x000000D8
 248 #define V3_MAIL_RD_STAT         0x000000DA
 249 #define V3_QBA_MAP              0x000000DC
 250
 251 /* SYSTEM register bits */
 252 #define V3_SYSTEM_M_RST_OUT             (1 << 15)
 253 #define V3_SYSTEM_M_LOCK                (1 << 14)
 254
 255 /*  PCI_CFG bits */
 256 #define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
 257 #define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
 258 #define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
 259
 260 /* PCI MAP register bits (PCI -> Local bus) */
 261 #define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
 262 #define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
 263 #define V3_PCI_MAP_M_ROM_SIZE           (1 << 11 | 1 << 10)
 264 #define V3_PCI_MAP_M_SWAP               (1 << 9 | 1 << 8)
 265 #define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
 266 #define V3_PCI_MAP_M_REG_EN             (1 << 1)
 267 #define V3_PCI_MAP_M_ENABLE             (1 << 0)
 268
 269 /* 9 => 512M window size */
 270 #define V3_PCI_MAP_M_ADR_SIZE_512M      0x00000090
 271
 272 /* A => 1024M window size */
 273 #define V3_PCI_MAP_M_ADR_SIZE_1024M     0x000000A0
 274
 275 /* LB_BASE register bits (Local bus -> PCI) */
 276 #define V3_LB_BASE_M_MAP_ADR            0xFFF00000
 277 #define V3_LB_BASE_M_SWAP               (1 << 8 | 1 << 9)
 278 #define V3_LB_BASE_M_ADR_SIZE           0x000000F0
 279 #define V3_LB_BASE_M_PREFETCH           (1 << 3)
 280 #define V3_LB_BASE_M_ENABLE             (1 << 0)
 281
 282 /* PCI COMMAND REGISTER bits */
 283 #define V3_COMMAND_M_FBB_EN             (1 << 9)
 284 #define V3_COMMAND_M_SERR_EN            (1 << 8)
 285 #define V3_COMMAND_M_PAR_EN             (1 << 6)
 286 #define V3_COMMAND_M_MASTER_EN          (1 << 2)
 287 #define V3_COMMAND_M_MEM_EN             (1 << 1)
 288 #define V3_COMMAND_M_IO_EN              (1 << 0)
 289
 290 #define INTEGRATOR_SC_BASE              0x11000000
 291 #define INTEGRATOR_SC_PCIENABLE_OFFSET  0x18
 292 #define INTEGRATOR_SC_PCIENABLE \
 293                         (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
 294
 295 #endif /* CONFIG_PCI */
 296 /*-----------------------------------------------------------------------
 297  * There are various dependencies on the core module (CM) fitted
 298  * Users should refer to their CM user guide
 299  * - when porting adjust u-boot/Makefile accordingly
 300  *   to define the necessary CONFIG_ s for the CM involved
 301  * see e.g. integratorcp_CM926EJ-S_config
 302  */
 303 #include "armcoremodule.h"
 304
 305 #endif  /* __CONFIG_H */