include/configs/intip.h

   1 /*
   2  * (C) Copyright 2009
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * Based on include/configs/canyonlands.h
   6  * (C) Copyright 2008
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 /*
  13  * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center
  14  */
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  */
  21 /*
  22  * This config file is used for CompactCenter(codename intip) and DevCon-Center
  23  */
  24 #define CONFIG_460EX            1       /* Specific PPC460EX            */
  25 #ifdef CONFIG_DEVCONCENTER
  26 #define CONFIG_HOSTNAME         devconcenter
  27 #else
  28 #define CONFIG_HOSTNAME         intip
  29 #endif
  30 #define CONFIG_440              1
  31
  32 #ifndef CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  34 #endif
  35
  36 /*
  37  * Include common defines/options for all AMCC eval boards
  38  */
  39 #include "amcc-common.h"
  40
  41 #define CONFIG_SYS_CLK_FREQ     66666667        /* external freq to pll */
  42
  43 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_early_init_f */
  44 #define CONFIG_BOARD_EARLY_INIT_R       1       /* Call board_early_init_r */
  45 #define CONFIG_MISC_INIT_R              1       /* Call misc_init_r */
  46 #define CONFIG_BOARD_TYPES              1       /* support board types */
  47 #define CFG_ALT_MEMTEST
  48
  49 /*
  50  * Base addresses -- Note these are effective addresses where the
  51  * actual resources get mapped (not physical addresses)
  52  */
  53 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory */
  54 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs */
  55 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  56
  57 /* EBC stuff */
  58 #ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
  59 #define CONFIG_SYS_FLASH_BASE           0xF8000000      /* later mapped here */
  60 #define CONFIG_SYS_FLASH_SIZE           (128 << 20)
  61 #else
  62 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* later mapped here */
  63 #define CONFIG_SYS_FLASH_SIZE           (64 << 20)
  64 #endif
  65
  66 #define CONFIG_SYS_NVRAM_BASE           0xE0000000
  67 #define CONFIG_SYS_UART_BASE            0xE0100000
  68 #define CONFIG_SYS_IO_BASE              0xE0200000
  69
  70 #define CONFIG_SYS_BOOT_BASE_ADDR       0xFF000000      /* EBC Boot Space */
  71 #define CONFIG_SYS_FLASH_BASE_PHYS_H    0x4
  72 #ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
  73 #define CONFIG_SYS_FLASH_BASE_PHYS_L    0xC8000000
  74 #else
  75 #define CONFIG_SYS_FLASH_BASE_PHYS_L    0xCC000000
  76 #endif
  77 #define CONFIG_SYS_FLASH_BASE_PHYS \
  78         (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
  79         | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
  80
  81 #define CONFIG_SYS_OCM_BASE             0xE3000000      /* OCM: 64k */
  82 #define CONFIG_SYS_SRAM_BASE            0xE8000000      /* SRAM: 256k */
  83 #define CONFIG_SYS_SRAM_SIZE            (256 << 10)
  84 #define CONFIG_SYS_LOCAL_CONF_REGS      0xEF000000
  85
  86 #define CONFIG_SYS_AHB_BASE             0xE2000000      /* int. AHB periph. */
  87
  88 /*
  89  * Initial RAM & stack pointer (placed in OCM)
  90  */
  91 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM */
  92 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  93 #define CONFIG_SYS_GBL_DATA_OFFSET \
  94         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  95 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  96
  97 /*
  98  * Serial Port
  99  */
 100 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 101
 102 /*
 103  * Environment
 104  */
 105 /*
 106  * Define here the location of the environment variables (FLASH).
 107  */
 108 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 109 #define CONFIG_SYS_NOR_CS               0       /* NOR chip connected to CSx */
 110
 111 /*
 112  * FLASH related
 113  */
 114 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 115 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 116 #define CONFIG_SYS_FLASH_CFI_AMD_RESET  1       /* Use AMD reset cmd */
 117
 118 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 119 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 120 #ifdef CONFIG_DEVCONCENTER
 121 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* max num of sectors per chip*/
 122 #else
 123 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 124 #endif
 125
 126 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 127 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 128
 129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* buff'd writes (20x faster) */
 130 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 131
 132 #ifdef CONFIG_ENV_IS_IN_FLASH
 133 #define CONFIG_ENV_SECT_SIZE    0x20000         /* size of one complete sector*/
 134 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 135 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector */
 136
 137 /* Address and size of Redundant Environment Sector     */
 138 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 139 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 140 #endif /* CONFIG_ENV_IS_IN_FLASH */
 141
 142 /*
 143  * DDR SDRAM
 144  */
 145
 146 #define CONFIG_AUTOCALIB        "silent\0"      /* default is non-verbose    */
 147
 148 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration   */
 149 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 150 #undef CONFIG_PPC4xx_DDR_METHOD_A
 151
 152 /* DDR1/2 SDRAM Device Control Register Data Values */
 153 /* Memory Queue */
 154 #define CONFIG_SYS_SDRAM_R0BAS          0x0000f800
 155 #define CONFIG_SYS_SDRAM_R1BAS          0x00000000
 156 #define CONFIG_SYS_SDRAM_R2BAS          0x00000000
 157 #define CONFIG_SYS_SDRAM_R3BAS          0x00000000
 158 #define CONFIG_SYS_SDRAM_PLBADDULL      0x00000000
 159 #define CONFIG_SYS_SDRAM_PLBADDUHB      0x00000008
 160 #define CONFIG_SYS_SDRAM_CONF1LL        0x80001C00
 161 #define CONFIG_SYS_SDRAM_CONF1HB        0x80001C80
 162 #define CONFIG_SYS_SDRAM_CONFPATHB      0x10a68000
 163
 164 /* SDRAM Controller */
 165 #define CONFIG_SYS_SDRAM0_MB0CF         0x00000201
 166 #define CONFIG_SYS_SDRAM0_MB1CF         0x00000000
 167 #define CONFIG_SYS_SDRAM0_MB2CF         0x00000000
 168 #define CONFIG_SYS_SDRAM0_MB3CF         0x00000000
 169 #define CONFIG_SYS_SDRAM0_MCOPT1        0x05120000
 170 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 171 #define CONFIG_SYS_SDRAM0_MODT0         0x00000000
 172 #define CONFIG_SYS_SDRAM0_MODT1         0x00000000
 173 #define CONFIG_SYS_SDRAM0_MODT2         0x00000000
 174 #define CONFIG_SYS_SDRAM0_MODT3         0x00000000
 175 #define CONFIG_SYS_SDRAM0_CODT          0x00000020
 176 #define CONFIG_SYS_SDRAM0_RTR           0x06180000
 177 #define CONFIG_SYS_SDRAM0_INITPLR0      0xA8380000
 178 #define CONFIG_SYS_SDRAM0_INITPLR1      0x81900400
 179 #define CONFIG_SYS_SDRAM0_INITPLR2      0x81020000
 180 #define CONFIG_SYS_SDRAM0_INITPLR3      0x81030000
 181 #define CONFIG_SYS_SDRAM0_INITPLR4      0x81010002
 182 #define CONFIG_SYS_SDRAM0_INITPLR5      0xE4000552
 183 #define CONFIG_SYS_SDRAM0_INITPLR6      0x81900400
 184 #define CONFIG_SYS_SDRAM0_INITPLR7      0x8A880000
 185 #define CONFIG_SYS_SDRAM0_INITPLR8      0x8A880000
 186 #define CONFIG_SYS_SDRAM0_INITPLR9      0x8A880000
 187 #define CONFIG_SYS_SDRAM0_INITPLR10     0x8A880000
 188 #define CONFIG_SYS_SDRAM0_INITPLR11     0x81000452
 189 #define CONFIG_SYS_SDRAM0_INITPLR12     0x81010382
 190 #define CONFIG_SYS_SDRAM0_INITPLR13     0x81010002
 191 #define CONFIG_SYS_SDRAM0_INITPLR14     0x00000000
 192 #define CONFIG_SYS_SDRAM0_INITPLR15     0x00000000
 193 #define CONFIG_SYS_SDRAM0_RQDC          0x80000038
 194 #define CONFIG_SYS_SDRAM0_RFDC          0x00000257
 195 #define CONFIG_SYS_SDRAM0_RDCC          0x40000000
 196 #define CONFIG_SYS_SDRAM0_DLCR          0x00000000
 197 #define CONFIG_SYS_SDRAM0_CLKTR         0x40000000
 198 #define CONFIG_SYS_SDRAM0_WRDTR         0x86000823
 199 #define CONFIG_SYS_SDRAM0_SDTR1         0x80201000
 200 #define CONFIG_SYS_SDRAM0_SDTR2         0x32204232
 201 #define CONFIG_SYS_SDRAM0_SDTR3         0x090C0D15
 202 #define CONFIG_SYS_SDRAM0_MMODE         0x00000452
 203 #define CONFIG_SYS_SDRAM0_MEMODE        0x00000002
 204
 205 #define CONFIG_SYS_MBYTES_SDRAM 256     /* 256MB */
 206
 207 /*
 208  * I2C
 209  */
 210 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 211
 212 #define CONFIG_SYS_I2C_EEPROM_ADDR              (0xa8>>1)
 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 216
 217 /* I2C bootstrap EEPROM */
 218 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x54
 219 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 220 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 221
 222 /* I2C SYSMON */
 223 #define CONFIG_DTT_LM63         1       /* National LM63        */
 224 #define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
 225 #define CONFIG_DTT_PWM_LOOKUPTABLE      \
 226         { { 40, 10 }, { 50, 20 }, { 60, 40 } }
 227 #define CONFIG_DTT_TACH_LIMIT   0xa10
 228
 229 /* RTC configuration */
 230 #define CONFIG_RTC_DS1337       1
 231 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 232
 233 /*
 234  * Ethernet
 235  */
 236 #define CONFIG_IBM_EMAC4_V4     1
 237
 238 #define CONFIG_HAS_ETH0
 239 #define CONFIG_HAS_ETH1
 240
 241 #define CONFIG_PHY_ADDR         2       /* PHY address, See schematics  */
 242 #define CONFIG_PHY1_ADDR        3
 243
 244 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 245 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 246 #define CONFIG_PHY_DYNAMIC_ANEG 1
 247
 248 /*
 249  * USB-OHCI
 250  */
 251 #define CONFIG_USB_OHCI_NEW
 252 #undef CONFIG_SYS_OHCI_BE_CONTROLLER    /* 460EX has little endian descriptors*/
 253 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
 254 #define CONFIG_SYS_OHCI_USE_NPS         /* force NoPowerSwitching mode */
 255 #define CONFIG_SYS_USB_OHCI_REGS_BASE   (CONFIG_SYS_AHB_BASE | 0xd0000)
 256 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 257 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 258
 259 /*
 260  * Default environment variables
 261  */
 262 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 263         CONFIG_AMCC_DEF_ENV                                             \
 264         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 265         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 266         "kernel_addr=fc000000\0"                                        \
 267         "fdt_addr=fc1e0000\0"                                           \
 268         "ramdisk_addr=fc200000\0"                                       \
 269         "pciconfighost=1\0"                                             \
 270         "pcie_mode=RP:RP\0"                                             \
 271         ""
 272
 273 /*
 274  * Commands additional to the ones defined in amcc-common.h
 275  */
 276 #define CONFIG_CMD_CHIP_CONFIG
 277 #define CONFIG_CMD_DATE
 278 #define CONFIG_CMD_DTT
 279 #define CONFIG_CMD_PCI
 280 #define CONFIG_CMD_SDRAM
 281
 282 /* Partitions */
 283 #define CONFIG_MAC_PARTITION
 284 #define CONFIG_DOS_PARTITION
 285 #define CONFIG_ISO_PARTITION
 286
 287 /*
 288  * PCI stuff
 289  */
 290 /* General PCI */
 291 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 292 #define CONFIG_PCI_PNP                  /* do pci plug-and-play   */
 293 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 294 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 295 #define CONFIG_PCI_DISABLE_PCIE
 296
 297 /* Board-specific PCI */
 298 #define CONFIG_SYS_PCI_TARGET_INIT      /* let board init pci target */
 299 #undef  CONFIG_SYS_PCI_MASTER_INIT
 300
 301 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM */
 302 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 303
 304 /*
 305  * External Bus Controller (EBC) Setup
 306  */
 307
 308 /*
 309  * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
 310  * boot EBC mapping only supports a maximum of 16MBytes
 311  * (4.ff00.0000 - 4.ffff.ffff).
 312  * To solve this problem, the FLASH has to get remapped to another
 313  * EBC address which accepts bigger regions:
 314  *
 315  * 0xfc00.0000 -> 4.cc00.0000
 316  */
 317
 318 /* Memory Bank 0 (NOR-FLASH) initialization */
 319 #define CONFIG_SYS_EBC_PB0AP            0x10055e00
 320 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
 321
 322 /* Memory Bank 1 (NVRAM) initialization */
 323 #define CONFIG_SYS_EBC_PB1AP            0x02815480
 324 /* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
 325 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NVRAM_BASE | 0x18000)
 326
 327 /* Memory Bank 2 (UART) initialization  */
 328 #define CONFIG_SYS_EBC_PB2AP            0x02815480
 329 /* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
 330 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_UART_BASE | 0x1A000)
 331
 332 /* Memory Bank 3 (IO) initialization */
 333 #define CONFIG_SYS_EBC_PB3AP            0x02815480
 334 /* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
 335 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_IO_BASE | 0x1A000)
 336
 337 /*
 338  * PPC4xx GPIO Configuration
 339  */
 340 /* 460EX: Use USB configuration */
 341 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 342 {                                                                                       \
 343 /* GPIO Core 0 */                                                                       \
 344 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0)      USB2HostD(0)    */      \
 345 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1)      USB2HostD(1)    */      \
 346 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2)      USB2HostD(2)    */      \
 347 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3)      USB2HostD(3)    */      \
 348 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4)      USB2HostD(4)    */      \
 349 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5)      USB2HostD(5)    */      \
 350 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6)      USB2HostD(6)    */      \
 351 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7)      USB2HostD(7)    */      \
 352 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0)      USB2OTGD(0)     */      \
 353 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1)      USB2OTGD(1)     */      \
 354 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)     USB2OTGD(2)     */      \
 355 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)     USB2OTGD(3)     */      \
 356 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)     USB2OTGD(4)     */      \
 357 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)     USB2OTGD(5)     */      \
 358 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)     USB2OTGD(6)     */      \
 359 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)     USB2OTGD(7)     */      \
 360 {GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER       USB2HostStop    */      \
 361 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD         USB2HostNext    */      \
 362 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER       USB2HostDir     */      \
 363 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN       USB2OTGStop     */      \
 364 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS        USB2OTGNext     */      \
 365 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV       USB2OTGDir      */      \
 366 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                          */      \
 367 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                          */      \
 368 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                          */      \
 369 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE                          */      \
 370 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE                          */      \
 371 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)                         */      \
 372 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)                         */      \
 373 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)                         */      \
 374 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0        DMAReq2         IRQ(7)*/ \
 375 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1        DMAAck2         IRQ(8)*/ \
 376 },                                                                                      \
 377 {                                                                                       \
 378 /* GPIO Core 1 */                                                                       \
 379 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2        EOT2/TC2        IRQ(9)*/ \
 380 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3        DMAReq3         IRQ(4)*/ \
 381 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 382 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 383 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3       UART3_SIN*/ \
 384 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EOT3/TC3        UART3_SOUT*/ \
 385 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 386 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 387 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)                         */      \
 388 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)                          */      \
 389 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)                          */      \
 390 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)          DMAReq1         IRQ(10)*/ \
 391 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)          DMAAck1         IRQ(11)*/ \
 392 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)          EOT/TC1         IRQ(12)*/ \
 393 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)     DMAReq0         IRQ(13)*/ \
 394 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)     DMAAck0         IRQ(14)*/ \
 395 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)     EOT/TC0         IRQ(15)*/ \
 396 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 397 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  USB_SERVICE_SUSPEND_N         */      \
 398 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51  SPI_CSS_N                     */      \
 399 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52  FPGA_PROGRAM_UC_N             */      \
 400 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  FPGA_INIT_UC_N                */      \
 401 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54  WD_STROBE                     */      \
 402 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  LED_2_OUT                     */      \
 403 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56  LED_1_OUT                     */      \
 404 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 405 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 406 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 407 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 408 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61  STARTUP_FINISHED_N            */      \
 409 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62  STARTUP_FINISHED              */      \
 410 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  SERVICE_PORT_ACTIVE           */      \
 411 }                                                                                       \
 412 }
 413
 414 #endif  /* __CONFIG_H */