include/configs/io.h

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12 #define CONFIG_IO               1       /*  on a Io board */
  13
  14 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16 /*
  17  * Include common defines/options for all AMCC eval boards
  18  */
  19 #define CONFIG_HOSTNAME         io
  20 #include "amcc-common.h"
  21
  22 #define CONFIG_BOARD_EARLY_INIT_F
  23 #define CONFIG_BOARD_EARLY_INIT_R
  24 #define CONFIG_MISC_INIT_R
  25 #define CONFIG_LAST_STAGE_INIT
  26
  27 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  28
  29 /*
  30  * Configure PLL
  31  */
  32 #define PLLMR0_DEFAULT PLLMR0_266_133_66
  33 #define PLLMR1_DEFAULT PLLMR1_266_133_66
  34
  35 /* new uImage format support */
  36 #define CONFIG_FIT_DISABLE_SHA256
  37
  38 #define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  39
  40 /*
  41  * Default environment variables
  42  */
  43 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  44         CONFIG_AMCC_DEF_ENV                                             \
  45         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  46         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  47         "kernel_addr=fc000000\0"                                        \
  48         "fdt_addr=fc1e0000\0"                                           \
  49         "ramdisk_addr=fc200000\0"                                       \
  50         ""
  51
  52 #define CONFIG_PHY_ADDR         4       /* PHY address                  */
  53 #define CONFIG_HAS_ETH0
  54 #define CONFIG_HAS_ETH1
  55 #define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  56 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
  57
  58 /*
  59  * Commands additional to the ones defined in amcc-common.h
  60  */
  61 #define CONFIG_CMD_DTT
  62 #undef CONFIG_CMD_DIAG
  63 #undef CONFIG_CMD_EEPROM
  64 #undef CONFIG_CMD_IRQ
  65
  66 /*
  67  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  68  */
  69 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  70
  71 /* SDRAM timings used in datasheet */
  72 #define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  73 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  74 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  75 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  76 #define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  77
  78 /*
  79  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  80  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  81  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  82  * The Linux BASE_BAUD define should match this configuration.
  83  *    baseBaud = cpuClock/(uartDivisor*16)
  84  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  85  * set Linux BASE_BAUD to 403200.
  86  */
  87 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  88 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK     /* external serial clock */
  89 #undef  CONFIG_SYS_405_UART_ERRATA_59   /* 405GP/CR Rev. D silicon */
  90 #define CONFIG_SYS_BASE_BAUD            691200
  91
  92 /*
  93  * I2C stuff
  94  */
  95 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
  96
  97 /* Temp sensor/hwmon/dtt */
  98 #define CONFIG_DTT_LM63         1       /* National LM63        */
  99 #define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
 100 #define CONFIG_DTT_PWM_LOOKUPTABLE      \
 101                 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
 102 #define CONFIG_DTT_TACH_LIMIT   0xa10
 103
 104 /*
 105  * FLASH organization
 106  */
 107 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 108 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 109
 110 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 111 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 112
 113 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 114 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 115
 116 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 117 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 118
 119 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 120
 121 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 122 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 123
 124 #ifdef CONFIG_ENV_IS_IN_FLASH
 125 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 126 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 127 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 128
 129 /* Address and size of Redundant Environment Sector     */
 130 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 131 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 132 #endif
 133
 134 /* Gbit PHYs */
 135 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 136 #define CONFIG_BITBANGMII_MULTI
 137
 138 #define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13) /* our MDIO is GPIO0 */
 139 #define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)  /* our MDC  is GPIO7 */
 140
 141 #define CONFIG_SYS_GBIT_MII_BUSNAME     "io_miiphy"
 142
 143 /*
 144  * PPC405 GPIO Configuration
 145  */
 146 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 147 { \
 148 /* GPIO Core 0 */ \
 149 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 150 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 151 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 152 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 153 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 154 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 155 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 156 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7   TS5 */ \
 157 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 158 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 159 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 160 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 161 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 162 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 163 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 164 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 165 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 166 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 167 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 168 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 169 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 170 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 171 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 172 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 173 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 174 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 175 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 176 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 177 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 178 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 179 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 180 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 181 } \
 182 }
 183
 184 /*
 185  * Definitions for initial stack pointer and data area (in data cache)
 186  */
 187 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 188 #define CONFIG_SYS_TEMP_STACK_OCM        1
 189
 190 /* On Chip Memory location */
 191 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 192 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 193 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 194 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE
 195
 196 #define CONFIG_SYS_GBL_DATA_OFFSET \
 197         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 198 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 199
 200 /*
 201  * External Bus Controller (EBC) Setup
 202  */
 203
 204 /* Memory Bank 0 (NOR-FLASH) initialization */
 205 #define CONFIG_SYS_EBC_PB0AP            0xa382a880
 206 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
 207 #define CONFIG_SYS_EBC_PB0CR            0xFC0DA000
 208
 209 /* Memory Bank 1 (NVRAM) initializatio */
 210 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 211 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 212 #define CONFIG_SYS_EBC_PB1CR            0x7f318000
 213
 214 /* Memory Bank 2 (FPGA) initialization */
 215 #define CONFIG_SYS_FPGA0_BASE           0x7f100000
 216 #define CONFIG_SYS_EBC_PB2AP            0x02025080
 217 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 218 #define CONFIG_SYS_EBC_PB2CR            0x7f11a000
 219
 220 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 221 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 222
 223 #define CONFIG_SYS_FPGA_COUNT           1
 224
 225 #define CONFIG_SYS_FPGA_PTR \
 226         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
 227
 228 #define CONFIG_SYS_FPGA_COMMON
 229
 230 /* Memory Bank 3 (Latches) initialization */
 231 #define CONFIG_SYS_LATCH_BASE           0x7f200000
 232 #define CONFIG_SYS_EBC_PB3AP            0xa2015480
 233 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 234 #define CONFIG_SYS_EBC_PB3CR            0x7f21a000
 235
 236 #define CONFIG_SYS_LATCH0_RESET         0xffff
 237 #define CONFIG_SYS_LATCH0_BOOT          0xffff
 238 #define CONFIG_SYS_LATCH1_RESET         0xffbf
 239 #define CONFIG_SYS_LATCH1_BOOT          0xffff
 240
 241 #endif  /* __CONFIG_H */