include/configs/io.h

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  28 #define CONFIG_4xx              1       /*  member of PPC4xx family */
  29 #define CONFIG_IO               1       /*  on a Io board */
  30
  31 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  32
  33 /*
  34  * Include common defines/options for all AMCC eval boards
  35  */
  36 #define CONFIG_HOSTNAME         io
  37 #define CONFIG_IDENT_STRING     " io 0.05"
  38 #include "amcc-common.h"
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F
  41 #define CONFIG_BOARD_EARLY_INIT_R
  42 #define CONFIG_MISC_INIT_R
  43 #define CONFIG_LAST_STAGE_INIT
  44
  45 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  46
  47 /*
  48  * Configure PLL
  49  */
  50 #define PLLMR0_DEFAULT PLLMR0_266_133_66
  51 #define PLLMR1_DEFAULT PLLMR1_266_133_66
  52
  53 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* ignore keypress on bootdelay==0 */
  54 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
  55 #define CONFIG_AUTOBOOT_STOP_STR " "
  56
  57 /* new uImage format support */
  58 #define CONFIG_FIT
  59 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  60
  61 #define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  62
  63 /*
  64  * Default environment variables
  65  */
  66 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  67         CONFIG_AMCC_DEF_ENV                                             \
  68         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  69         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  70         "kernel_addr=fc000000\0"                                        \
  71         "fdt_addr=fc1e0000\0"                                           \
  72         "ramdisk_addr=fc200000\0"                                       \
  73         ""
  74
  75 #define CONFIG_PHY_ADDR         4       /* PHY address                  */
  76 #define CONFIG_HAS_ETH0
  77 #define CONFIG_HAS_ETH1
  78 #define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  79 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
  80
  81 /*
  82  * Commands additional to the ones defined in amcc-common.h
  83  */
  84 #define CONFIG_CMD_CACHE
  85 #define CONFIG_CMD_DTT
  86 #undef CONFIG_CMD_EEPROM
  87
  88 /*
  89  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  90  */
  91 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  92
  93 /* SDRAM timings used in datasheet */
  94 #define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  95 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  96 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  97 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  98 #define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  99
 100 /*
 101  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 102  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 103  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
 104  * The Linux BASE_BAUD define should match this configuration.
 105  *    baseBaud = cpuClock/(uartDivisor*16)
 106  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 107  * set Linux BASE_BAUD to 403200.
 108  */
 109 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 110 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK     /* external serial clock */
 111 #undef  CONFIG_SYS_405_UART_ERRATA_59   /* 405GP/CR Rev. D silicon */
 112 #define CONFIG_SYS_BASE_BAUD            691200
 113
 114 /*
 115  * I2C stuff
 116  */
 117 #define CONFIG_SYS_I2C_SPEED            100000
 118
 119 /* Temp sensor/hwmon/dtt */
 120 #define CONFIG_DTT_LM63         1       /* National LM63        */
 121 #define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
 122 #define CONFIG_DTT_PWM_LOOKUPTABLE      \
 123                 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
 124 #define CONFIG_DTT_TACH_LIMIT   0xa10
 125
 126 /*
 127  * FLASH organization
 128  */
 129 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 130 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 131
 132 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 133 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 134
 135 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 136 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 137
 138 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 139 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 140
 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 142 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protect */
 143
 144 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 145 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 146
 147 #ifdef CONFIG_ENV_IS_IN_FLASH
 148 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 149 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 150 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 151
 152 /* Address and size of Redundant Environment Sector     */
 153 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 154 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 155 #endif
 156
 157 /* Gbit PHYs */
 158 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 159 #define CONFIG_BITBANGMII_MULTI
 160
 161 #define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13) /* our MDIO is GPIO0 */
 162 #define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)  /* our MDC  is GPIO7 */
 163
 164 #define CONFIG_SYS_GBIT_MII_BUSNAME     "io_miiphy"
 165
 166 /*
 167  * PPC405 GPIO Configuration
 168  */
 169 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 170 { \
 171 /* GPIO Core 0 */ \
 172 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 173 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 174 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 175 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 176 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 177 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 178 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 179 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7   TS5 */ \
 180 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 181 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 182 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 183 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 184 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 185 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 186 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 187 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 188 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 189 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 190 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 191 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 192 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 193 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 194 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 195 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 196 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 197 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 198 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 199 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 200 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 201 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 202 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 203 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 204 } \
 205 }
 206
 207 /*
 208  * Definitions for initial stack pointer and data area (in data cache)
 209  */
 210 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 211 #define CONFIG_SYS_TEMP_STACK_OCM        1
 212
 213 /* On Chip Memory location */
 214 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 215 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 216 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 217 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
 218
 219 #define CONFIG_SYS_GBL_DATA_SIZE        128  /* size/bytes res'd for init data*/
 220 #define CONFIG_SYS_GBL_DATA_OFFSET \
 221         (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 222 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 223
 224 /*
 225  * External Bus Controller (EBC) Setup
 226  */
 227
 228 /* Memory Bank 0 (NOR-FLASH) initialization */
 229 #define CONFIG_SYS_EBC_PB0AP            0xa382a880
 230 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
 231 #define CONFIG_SYS_EBC_PB0CR            0xFC0DA000
 232
 233 /* Memory Bank 1 (NVRAM) initializatio */
 234 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 235 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 236 #define CONFIG_SYS_EBC_PB1CR            0x7f318000
 237
 238 /* Memory Bank 2 (FPGA) initialization */
 239 #define CONFIG_SYS_FPGA0_BASE           0x7f100000
 240 #define CONFIG_SYS_EBC_PB2AP            0x02025080
 241 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 242 #define CONFIG_SYS_EBC_PB2CR            0x7f11a000
 243
 244 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 245 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 246
 247 #define CONFIG_SYS_FPGA_COUNT           1
 248
 249 /* Memory Bank 3 (Latches) initialization */
 250 #define CONFIG_SYS_LATCH_BASE           0x7f200000
 251 #define CONFIG_SYS_EBC_PB3AP            0xa2015480
 252 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 253 #define CONFIG_SYS_EBC_PB3CR            0x7f21a000
 254
 255 #define CONFIG_SYS_LATCH0_RESET         0xffff
 256 #define CONFIG_SYS_LATCH0_BOOT          0xffff
 257 #define CONFIG_SYS_LATCH1_RESET         0xffbf
 258 #define CONFIG_SYS_LATCH1_BOOT          0xffff
 259
 260 #endif  /* __CONFIG_H */