include/configs/iocon.h

   1 /*
   2  * (C) Copyright 2010
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12 #define CONFIG_IOCON            1       /*  on a IoCon board */
  13
  14 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16 /*
  17  * Include common defines/options for all AMCC eval boards
  18  */
  19 #define CONFIG_HOSTNAME         iocon
  20 #include "amcc-common.h"
  21
  22 /* Reclaim some space. */
  23 #undef CONFIG_SYS_LONGHELP
  24
  25 #define CONFIG_BOARD_EARLY_INIT_R
  26 #define CONFIG_LAST_STAGE_INIT
  27
  28 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  29
  30 /*
  31  * Configure PLL
  32  */
  33 #define PLLMR0_DEFAULT PLLMR0_266_133_66
  34 #define PLLMR1_DEFAULT PLLMR1_266_133_66
  35
  36 /* new uImage format support */
  37 #define CONFIG_FIT_DISABLE_SHA256
  38
  39 #define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  40
  41 /*
  42  * Default environment variables
  43  */
  44 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  45         CONFIG_AMCC_DEF_ENV                                             \
  46         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  47         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  48         "kernel_addr=fc000000\0"                                        \
  49         "fdt_addr=fc1e0000\0"                                           \
  50         "ramdisk_addr=fc200000\0"                                       \
  51         ""
  52
  53 #define CONFIG_PHY_ADDR         4       /* PHY address                  */
  54 #define CONFIG_HAS_ETH0
  55 #define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
  56
  57 /*
  58  * Commands additional to the ones defined in amcc-common.h
  59  */
  60 #define CONFIG_CMD_FPGAD
  61 #undef CONFIG_CMD_EEPROM
  62 #undef CONFIG_CMD_IRQ
  63
  64 /*
  65  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  66  */
  67 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  68
  69 /* SDRAM timings used in datasheet */
  70 #define CONFIG_SYS_SDRAM_CL             3       /* CAS latency */
  71 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  72 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE period */
  73 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  74 #define CONFIG_SYS_SDRAM_tRFC          66       /* Auto refresh period */
  75
  76 /*
  77  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  78  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  79  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  80  * The Linux BASE_BAUD define should match this configuration.
  81  *    baseBaud = cpuClock/(uartDivisor*16)
  82  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  83  * set Linux BASE_BAUD to 403200.
  84  */
  85 #define CONFIG_CONS_INDEX               1       /* Use UART0 */
  86 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK             /* external serial clock */
  87 #undef  CONFIG_SYS_405_UART_ERRATA_59           /* 405GP/CR Rev. D silicon */
  88 #define CONFIG_SYS_BASE_BAUD            691200
  89
  90 /*
  91  * I2C stuff
  92  */
  93 #define CONFIG_SYS_I2C
  94 #define CONFIG_SYS_I2C_PPC4XX
  95 #define CONFIG_SYS_I2C_PPC4XX_CH0
  96 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
  97 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
  98 #define CONFIG_SYS_I2C_IHS
  99
 100 #define CONFIG_SYS_I2C_SPEED            400000
 101 #define CONFIG_SYS_SPD_BUS_NUM          4
 102
 103 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 104 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 105
 106 #define CONFIG_SYS_I2C_IHS_CH0
 107 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 108 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 109 #define CONFIG_SYS_I2C_IHS_CH1
 110 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 111 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 112 #define CONFIG_SYS_I2C_IHS_CH2
 113 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 114 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 115 #define CONFIG_SYS_I2C_IHS_CH3
 116 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 117 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 118
 119 /*
 120  * Software (bit-bang) I2C driver configuration
 121  */
 122 #define CONFIG_SYS_I2C_SOFT
 123 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 124 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 125 #define I2C_SOFT_DECLARATIONS2
 126 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 127 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 128 #define I2C_SOFT_DECLARATIONS3
 129 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 130 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 131 #define I2C_SOFT_DECLARATIONS4
 132 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 133 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 134
 135 #define CONFIG_SYS_ICS8N3QV01_I2C               {5, 6, 7, 8}
 136 #define CONFIG_SYS_CH7301_I2C                   {5, 6, 7, 8}
 137 #define CONFIG_SYS_DP501_I2C                    {0, 1, 2, 3}
 138
 139 #ifndef __ASSEMBLY__
 140 void fpga_gpio_set(unsigned int bus, int pin);
 141 void fpga_gpio_clear(unsigned int bus, int pin);
 142 int fpga_gpio_get(unsigned int bus, int pin);
 143 #endif
 144
 145 #define I2C_ACTIVE      { }
 146 #define I2C_TRISTATE    { }
 147 #define I2C_READ \
 148         (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
 149 #define I2C_SDA(bit) \
 150         do { \
 151                 if (bit) \
 152                         fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
 153                 else \
 154                         fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
 155         } while (0)
 156 #define I2C_SCL(bit) \
 157         do { \
 158                 if (bit) \
 159                         fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
 160                 else \
 161                         fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
 162         } while (0)
 163 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 164
 165 /*
 166  * FLASH organization
 167  */
 168 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 169 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 170
 171 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 172 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 173
 174 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 175 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sectors per chip*/
 176
 177 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase/ms */
 178 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write/ms */
 179
 180 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buff'd writes */
 181
 182 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* 'E' for empty sector on flinfo */
 183 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* no warn upon unknown flash */
 184
 185 #ifdef CONFIG_ENV_IS_IN_FLASH
 186 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 187 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 188 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector */
 189
 190 /* Address and size of Redundant Environment Sector     */
 191 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 192 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 193 #endif
 194
 195 /*
 196  * PPC405 GPIO Configuration
 197  */
 198 #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO     Alternate1      */ \
 199 { \
 200 /* GPIO Core 0 */ \
 201 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast */ \
 202 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E */ \
 203 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E */ \
 204 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O */ \
 205 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O */ \
 206 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3 */ \
 207 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4 */ \
 208 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7   TS5 */ \
 209 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6 */ \
 210 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk */ \
 211 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1 */ \
 212 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2 */ \
 213 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3 */ \
 214 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4 */ \
 215 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03 */ \
 216 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04 */ \
 217 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05 */ \
 218 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0 */ \
 219 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1 */ \
 220 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2 */ \
 221 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3 */ \
 222 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4 */ \
 223 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5 */ \
 224 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6 */ \
 225 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD */ \
 226 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR */ \
 227 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI */ \
 228 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR */ \
 229 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx */ \
 230 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx */ \
 231 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 232 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 233 } \
 234 }
 235
 236 /*
 237  * Definitions for initial stack pointer and data area (in data cache)
 238  */
 239 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 240 #define CONFIG_SYS_TEMP_STACK_OCM        1
 241
 242 /* On Chip Memory location */
 243 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 244 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 245 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
 246 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE
 247
 248 #define CONFIG_SYS_GBL_DATA_OFFSET \
 249         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 250 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 251
 252 /*
 253  * External Bus Controller (EBC) Setup
 254  */
 255
 256 /* Memory Bank 0 (NOR-FLASH) initialization */
 257 #define CONFIG_SYS_EBC_PB0AP            0xa382a880
 258 #define CONFIG_SYS_EBC_PB0CR            0xFC0DA000
 259
 260 /* Memory Bank 1 (NVRAM) initializatio */
 261 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 262 #define CONFIG_SYS_EBC_PB1CR            0xFB858000
 263
 264 /* Memory Bank 2 (FPGA0) initialization */
 265 #define CONFIG_SYS_FPGA0_BASE           0x7f100000
 266 #define CONFIG_SYS_EBC_PB2AP            0x02825080
 267 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA0_BASE | 0x1a000)
 268
 269 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 270 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 271
 272 #define CONFIG_SYS_FPGA_COUNT           1
 273
 274 #define CONFIG_SYS_MCLINK_MAX           3
 275
 276 #define CONFIG_SYS_FPGA_PTR \
 277         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 278
 279 /* Memory Bank 3 (Latches) initialization */
 280 #define CONFIG_SYS_LATCH_BASE           0x7f200000
 281 #define CONFIG_SYS_EBC_PB3AP            0x02025080
 282 #define CONFIG_SYS_EBC_PB3CR            0x7f21a000
 283
 284 #define CONFIG_SYS_LATCH0_RESET         0xffef
 285 #define CONFIG_SYS_LATCH0_BOOT          0xffff
 286 #define CONFIG_SYS_LATCH1_RESET         0xffff
 287 #define CONFIG_SYS_LATCH1_BOOT          0xffff
 288
 289 /*
 290  * OSD Setup
 291  */
 292 #define CONFIG_SYS_MPC92469AC
 293 #define CONFIG_SYS_OSD_SCREENS          1
 294 #define CONFIG_SYS_DP501_DIFFERENTIAL
 295 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 296
 297 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 298 #define CONFIG_BITBANGMII_MULTI
 299
 300 #endif  /* __CONFIG_H */