include/configs/ip04.h

   1 /*
   2  * U-Boot - Configuration file for IP04 board (having BF532 processor)
   3  *
   4  * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
   5  *
   6  * Copyright (c) 2005-2010 Analog Devices Inc.
   7  *
   8  * (C) Copyright 2000-2004
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  *
  11  * Licensed under the GPL-2 or later.
  12  */
  13
  14 #ifndef __CONFIG_IP04_H__
  15 #define __CONFIG_IP04_H__
  16
  17 #include <asm/config-pre.h>
  18
  19 /*
  20  * Processor Settings
  21  */
  22 #define CONFIG_BFIN_CPU             bf532-0.5
  23 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_NAND
  24
  25 /*
  26  * Clock Settings
  27  *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  28  *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  29  */
  30 /* CONFIG_CLKIN_HZ is any value in Hz                                   */
  31 #define CONFIG_CLKIN_HZ                 10000000
  32 /* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  33 /*                                                1 = CLKIN / 2         */
  34 #define CONFIG_CLKIN_HALF               0
  35 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  36 /*                                                1 = bypass PLL        */
  37 #define CONFIG_PLL_BYPASS               0
  38 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  39 /* Values can range from 0-63 (where 0 means 64)                        */
  40 #define CONFIG_VCO_MULT                 40
  41 /* CCLK_DIV controls the core clock divider                             */
  42 /* Values can be 1, 2, 4, or 8 ONLY                                     */
  43 #define CONFIG_CCLK_DIV                 1
  44 /* SCLK_DIV controls the system clock divider                           */
  45 /* Values can range from 1-15                                           */
  46 #define CONFIG_SCLK_DIV                 3
  47
  48 /*
  49  * Memory Settings
  50  */
  51 #define CONFIG_MEM_ADD_WDTH     10
  52 #define CONFIG_MEM_SIZE         64
  53
  54 #define CONFIG_EBIU_SDRRC_VAL   0x408
  55 #define CONFIG_EBIU_SDGCTL_VAL  0x9111cd
  56
  57 #define CONFIG_EBIU_AMGCTL_VAL  0xFF
  58 #define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
  59 #define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
  60
  61 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)
  62 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  63
  64 /*
  65  * Network Settings
  66  */
  67 #define ADI_CMDS_NETWORK        1
  68 #define CONFIG_HOSTNAME         IP04
  69
  70 #define CONFIG_DRIVER_DM9000    1
  71 #define CONFIG_DM9000_NO_SROM
  72 #define CONFIG_DM9000_BASE      0x20100000
  73 #define DM9000_IO               CONFIG_DM9000_BASE
  74 #define DM9000_DATA             (CONFIG_DM9000_BASE + 2)
  75
  76 /*
  77  * Flash Settings
  78  */
  79 #define CONFIG_ENV_OVERWRITE    1
  80
  81 /*
  82  * SPI Settings
  83  */
  84 #define CONFIG_BFIN_SPI
  85 #define CONFIG_ENV_SPI_MAX_HZ   30000000
  86 #define CONFIG_SF_DEFAULT_SPEED 30000000
  87
  88 /*
  89  * Env Storage Settings
  90  */
  91 #define CONFIG_ENV_IS_IN_SPI_FLASH
  92 #define CONFIG_PREBOOT          "echo starting from spi flash"
  93 #define CONFIG_ENV_OFFSET       0x30000
  94 #define CONFIG_ENV_SIZE         0x10000
  95 #define CONFIG_ENV_SECT_SIZE    0x10000
  96
  97 /*
  98  * NAND Settings
  99  */
 100 #define CONFIG_NAND_PLAT
 101 #define CONFIG_SYS_NAND_BASE            0x20000000
 102 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 103
 104 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 105 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 106 #define BFIN_NAND_WRITE(addr, cmd) \
 107         do { \
 108                 bfin_write8(addr, cmd); \
 109                 SSYNC(); \
 110         } while (0)
 111
 112 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 113 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 114 #define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 115
 116 /*
 117  * Misc Settings
 118  */
 119 #define CONFIG_BAUDRATE         115200
 120 #define CONFIG_UART_CONSOLE     0
 121
 122 #undef CONFIG_SHOW_BOOT_PROGRESS
 123 /* Enable this if bootretry required; currently it's disabled */
 124 #define CONFIG_BOOT_RETRY_TIME  -1
 125 #define CONFIG_BOOTCOMMAND      "run nandboot"
 126
 127 /*
 128  * Pull in common ADI header for remaining command/environment setup
 129  */
 130 #include <configs/bfin_adi_common.h>
 131
 132 #endif