include/configs/jupiter.h

   1 /*
   2  * (C) Copyright 2007
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  33 #define CONFIG_MPC5200          1       /* especially an MPC5200 */
  34 #define CONFIG_JUPITER          1       /* ... on Jupiter board */
  35
  36 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  37
  38 #define CONFIG_BOARD_EARLY_INIT_R       1
  39 #define CONFIG_BOARD_EARLY_INIT_F       1
  40
  41 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  42 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  43
  44 /*
  45  * Serial console configuration
  46  */
  47 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  48 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  49 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  50
  51 /*
  52  * PCI Mapping:
  53  * 0x40000000 - 0x4fffffff - PCI Memory
  54  * 0x50000000 - 0x50ffffff - PCI IO Space
  55  */
  56 /*#define CONFIG_PCI            */
  57
  58 #if defined(CONFIG_PCI)
  59 #define CONFIG_PCI_PNP          1
  60 #define CONFIG_PCI_SCAN_SHOW    1
  61 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  62
  63 #define CONFIG_PCI_MEM_BUS      0x40000000
  64 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  65 #define CONFIG_PCI_MEM_SIZE     0x10000000
  66
  67 #define CONFIG_PCI_IO_BUS       0x50000000
  68 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  69 #define CONFIG_PCI_IO_SIZE      0x01000000
  70 #endif
  71
  72 #define CFG_XLB_PIPELINING      1
  73
  74 #define CONFIG_NET_MULTI        1
  75 #define CONFIG_MII              1
  76 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  77
  78 /* Partitions */
  79 #define CONFIG_MAC_PARTITION
  80 #define CONFIG_DOS_PARTITION
  81 #define CONFIG_ISO_PARTITION
  82
  83 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  84
  85
  86 /*
  87  * BOOTP options
  88  */
  89 #define CONFIG_BOOTP_BOOTFILESIZE
  90 #define CONFIG_BOOTP_BOOTPATH
  91 #define CONFIG_BOOTP_GATEWAY
  92 #define CONFIG_BOOTP_HOSTNAME
  93
  94
  95 /*
  96  * Command line configuration.
  97  */
  98 #include <config_cmd_default.h>
  99
 100 #define CONFIG_CMD_NFS
 101 #define CONFIG_CMD_SNTP
 102
 103 #if defined(CONFIG_PCI)
 104 #define CODFIG_CMD_PCI
 105 #endif
 106
 107
 108 /*
 109  * Autobooting
 110  */
 111 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 112
 113 #define CONFIG_PREBOOT  "echo;" \
 114         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 115         "echo"
 116
 117 #undef  CONFIG_BOOTARGS
 118
 119 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 120         "netdev=eth0\0"                                                 \
 121         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 122                 "nfsroot=${serverip}:${rootpath}\0"                     \
 123         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 124         "addip=setenv bootargs ${bootargs} "                            \
 125                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 126                 ":${hostname}:${netdev}:off panic=1\0"                  \
 127         "flash_nfs=run nfsargs addip addcons;"                          \
 128                 "bootm ${kernel_addr}\0"                                \
 129         "flash_self=run ramargs addip;"                                 \
 130                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 131         "addcons=setenv bootargs ${bootargs} console=${contyp},"        \
 132                 "${baudrate}\0"                                         \
 133         "contyp=ttyS0\0"                                                \
 134         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"    \
 135                 "bootm\0"                                               \
 136         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 137         "bootfile=/tftpboot/jupiter/uImage\0"                           \
 138         ""
 139
 140 #define CONFIG_BOOTCOMMAND      "run flash_self"
 141
 142 /*
 143  * IPB Bus clocking configuration.
 144  */
 145 #undef CFG_IPBSPEED_133                 /* define for 133MHz speed */
 146
 147 #if 0
 148 /* pass open firmware flat tree */
 149 #define CONFIG_OF_LIBFDT        1
 150 #define CONFIG_OF_BOARD_SETUP   1
 151
 152 #define OF_CPU                  "PowerPC,5200@0"
 153 #define OF_SOC                  "soc5200@f0000000"
 154 #define OF_TBCLK                (bd->bi_busfreq / 8)
 155 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 156 #endif
 157
 158 #if 0
 159 /*
 160  * I2C configuration
 161  */
 162 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 163 #define CFG_I2C_MODULE          2       /* Select I2C module #1 or #2 */
 164
 165 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 166 #define CFG_I2C_SLAVE           0x7F
 167
 168 /*
 169  * EEPROM configuration
 170  */
 171 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 172 #define CFG_I2C_EEPROM_ADDR_LEN         1
 173 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 174 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 175 #endif
 176
 177 /*
 178  * Flash configuration
 179  */
 180 #define CFG_FLASH_BASE          0xFF000000
 181 #define CFG_FLASH_SIZE          0x01000000
 182
 183 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 184
 185 #define CFG_ENV_ADDR            (TEXT_BASE + 0x40000) /* third sector */
 186
 187 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 188 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 189
 190 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks */
 191
 192 #define CFG_FLASH_CFI_DRIVER
 193 #define CFG_FLASH_CFI
 194 #define CFG_FLASH_EMPTY_INFO
 195 #define CFG_FLASH_CFI_WIDTH     FLASH_CFI_8BIT
 196 #define CFG_UPDATE_FLASH_SIZE   1
 197 #define CFG_FLASH_USE_BUFFER_WRITE      1
 198
 199 /*
 200  * Environment settings
 201  */
 202 #define CFG_ENV_IS_IN_FLASH     1
 203 #define CFG_ENV_SIZE            0x20000
 204 #define CFG_ENV_SECT_SIZE       0x20000
 205 #define CONFIG_ENV_OVERWRITE    1
 206
 207 /* Address and size of Redundant Environment Sector     */
 208 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 209 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 210
 211 /*
 212  * Memory map
 213  */
 214 #define CFG_MBAR                0xF0000000
 215 #define CFG_SDRAM_BASE          0x00000000
 216 #define CFG_DEFAULT_MBAR        0x80000000
 217
 218 /* Use SRAM until RAM will be available */
 219 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 220 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 221
 222
 223 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 224 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 225 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 226
 227 #define CFG_MONITOR_BASE    TEXT_BASE
 228 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 229 #   define CFG_RAMBOOT          1
 230 #endif
 231
 232 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 233 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 234 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 235
 236 /*
 237  * Ethernet configuration
 238  */
 239 #define CONFIG_MPC5xxx_FEC      1
 240 /*
 241  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 242  */
 243 /* #define CONFIG_FEC_10MBIT 1 */
 244 #define CONFIG_PHY_ADDR         0x00
 245
 246 /*
 247  * GPIO configuration
 248  */
 249 #define CFG_GPS_PORT_CONFIG     0x10000004
 250
 251 /*
 252  * Miscellaneous configurable options
 253  */
 254 #define CFG_LONGHELP                    /* undef to save memory     */
 255 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 256
 257 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 258 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 259 #ifdef  CFG_HUSH_PARSER
 260 #define CFG_PROMPT_HUSH_PS2     "> "
 261 #endif
 262 #if defined(CONFIG_CMD_KGDB)
 263 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 264 #else
 265 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 266 #endif
 267 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 268 #define CFG_MAXARGS             16              /* max number of command args   */
 269 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 270
 271 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 272 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 273 #define CFG_ALT_MEMTEST         1
 274
 275 #define CFG_LOAD_ADDR           0x200000        /* default load address */
 276
 277 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 278
 279 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 280 #if defined(CONFIG_CMD_KGDB)
 281 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 282 #endif
 283
 284 /*
 285  * Various low-level settings
 286  */
 287 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 288 #define CFG_HID0_FINAL          HID0_ICE
 289
 290 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 291 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 292 #define CFG_BOOTCS_CFG          0x00047801
 293 #define CFG_CS0_START           CFG_FLASH_BASE
 294 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 295
 296 #define CFG_CS_BURST            0x00000000
 297 #define CFG_CS_DEADCYCLE        0x33333333
 298
 299 #define CFG_RESET_ADDRESS       0xff000000
 300
 301 #endif /* __CONFIG_H */