include/configs/katmai.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /************************************************************************
  11  * katmai.h - configuration for AMCC Katmai (440SPe)
  12  ***********************************************************************/
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*-----------------------------------------------------------------------
  18  * High Level Configuration Options
  19  *----------------------------------------------------------------------*/
  20 #define CONFIG_KATMAI                   1       /* Board is Katmai      */
  21 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
  22 #define CONFIG_440                      1       /* ... PPC440 family    */
  23 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  24 #define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
  25 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  26 #define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
  27
  28 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  29
  30 /*
  31  * Enable this board for more than 2GB of SDRAM
  32  */
  33 #define CONFIG_PHYS_64BIT
  34 #define CONFIG_VERY_BIG_RAM
  35
  36 /*
  37  * Include common defines/options for all AMCC eval boards
  38  */
  39 #define CONFIG_HOSTNAME         katmai
  40 #include "amcc-common.h"
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
  43 #undef  CONFIG_SHOW_BOOT_PROGRESS
  44
  45 /*-----------------------------------------------------------------------
  46  * Base addresses -- Note these are effective addresses where the
  47  * actual resources get mapped (not physical addresses)
  48  *----------------------------------------------------------------------*/
  49 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH       */
  50 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
  51
  52 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  53 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  54 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  55
  56 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  57 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  58 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
  59
  60 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  61 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  62 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
  63 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  64 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  65 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
  66
  67 /* base address of inbound PCIe window */
  68 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
  69
  70 /* System RAM mapped to PCI space */
  71 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  72 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  73 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  74
  75 #define CONFIG_SYS_ACE_BASE             0xfe000000      /* Xilinx ACE controller - Compact Flash */
  76
  77 /*-----------------------------------------------------------------------
  78  * Initial RAM & stack pointer (placed in internal SRAM)
  79  *----------------------------------------------------------------------*/
  80 #define CONFIG_SYS_TEMP_STACK_OCM       1
  81 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
  82 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
  83 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM */
  84
  85 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  86 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  87
  88 /*-----------------------------------------------------------------------
  89  * Serial Port
  90  *----------------------------------------------------------------------*/
  91 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  92 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  93
  94 /*-----------------------------------------------------------------------
  95  * DDR SDRAM
  96  *----------------------------------------------------------------------*/
  97 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
  98 #define SPD_EEPROM_ADDRESS      {0x51, 0x52}    /* SPD i2c spd addresses*/
  99 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 100 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* optimal value found by GDA*/
 101 #undef  CONFIG_STRESS
 102
 103 /*-----------------------------------------------------------------------
 104  * I2C
 105  *----------------------------------------------------------------------*/
 106 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 107
 108 #define CONFIG_I2C_MULTI_BUS
 109 #define CONFIG_SYS_SPD_BUS_NUM          0       /* The I2C bus for SPD          */
 110
 111 #define IIC0_BOOTPROM_ADDR      0x50
 112 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 113
 114 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 115 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0x50)
 116 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 117 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 118 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 119
 120 /* I2C bootstrap EEPROM */
 121 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 122 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 123 #define CONFIG_4xx_CONFIG_BLOCKSIZE             8
 124
 125 /* I2C RTC */
 126 #define CONFIG_RTC_M41T11       1
 127 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC          */
 128 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 129 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
 130
 131 /* I2C DTT */
 132 #define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
 133 #define CONFIG_SYS_DTT_BUS_NUM          1       /* The I2C bus for DTT          */
 134 /*
 135  * standard dtt sensor configuration - bottom bit will determine local or
 136  * remote sensor of the ADM1021, the rest determines index into
 137  * CONFIG_SYS_DTT_ADM1021 array below.
 138  */
 139 #define CONFIG_DTT_SENSORS      { 0, 1 }
 140
 141 /*
 142  * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
 143  * there will be one entry in this array for each two (dummy) sensors in
 144  * CONFIG_DTT_SENSORS.
 145  *
 146  * For Katmai board:
 147  * - only one ADM1021
 148  * - i2c addr 0x18
 149  * - conversion rate 0x02 = 0.25 conversions/second
 150  * - ALERT ouput disabled
 151  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 152  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
 153  */
 154 #define CONFIG_SYS_DTT_ADM1021          { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
 155
 156 /*-----------------------------------------------------------------------
 157  * Environment
 158  *----------------------------------------------------------------------*/
 159 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 160
 161 /*
 162  * Default environment variables
 163  */
 164 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 165         CONFIG_AMCC_DEF_ENV                                             \
 166         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 167         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 168         "kernel_addr=ff000000\0"                                        \
 169         "fdt_addr=ff1e0000\0"                                           \
 170         "ramdisk_addr=ff200000\0"                                       \
 171         "pciconfighost=1\0"                                             \
 172         "pcie_mode=RP:RP:RP\0"                                          \
 173         ""
 174
 175 /*
 176  * Commands additional to the ones defined in amcc-common.h
 177  */
 178 #define CONFIG_CMD_CHIP_CONFIG
 179 #define CONFIG_CMD_DATE
 180 #define CONFIG_CMD_ECCTEST
 181 #define CONFIG_CMD_EXT2
 182 #define CONFIG_CMD_FAT
 183 #define CONFIG_CMD_PCI
 184 #define CONFIG_CMD_SDRAM
 185 #define CONFIG_CMD_SNTP
 186
 187 #define CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
 188 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 189 #define CONFIG_HAS_ETH0
 190 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 191 #define CONFIG_PHY_RESET_DELAY  1000
 192 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 193 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 194
 195 /*-----------------------------------------------------------------------
 196  * FLASH related
 197  *----------------------------------------------------------------------*/
 198 #define CONFIG_SYS_FLASH_CFI
 199 #define CONFIG_FLASH_CFI_DRIVER
 200 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 201 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 202
 203 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 204 #define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
 205 #define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
 206
 207 #undef  CONFIG_SYS_FLASH_CHECKSUM
 208 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 209 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 210
 211 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 212 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 213 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 214
 215 /* Address and size of Redundant Environment Sector     */
 216 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 217 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 218
 219 /*-----------------------------------------------------------------------
 220  * PCI stuff
 221  *-----------------------------------------------------------------------
 222  */
 223 /* General PCI */
 224 #define CONFIG_PCI                      /* include pci support          */
 225 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 226 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 227 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 228 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 229
 230 /* Board-specific PCI */
 231 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 232 #undef  CONFIG_SYS_PCI_MASTER_INIT
 233
 234 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 235 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 236 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 237
 238 /*
 239  *  NETWORK Support (PCI):
 240  */
 241 /* Support for Intel 82557/82559/82559ER chips. */
 242 #define CONFIG_EEPRO100
 243
 244 /*-----------------------------------------------------------------------
 245  * Xilinx System ACE support
 246  *----------------------------------------------------------------------*/
 247 #define CONFIG_SYSTEMACE        1       /* Enable SystemACE support     */
 248 #define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16         */
 249 #define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
 250 #define CONFIG_DOS_PARTITION    1
 251
 252 /*-----------------------------------------------------------------------
 253  * External Bus Controller (EBC) Setup
 254  *----------------------------------------------------------------------*/
 255
 256 /* Memory Bank 0 (Flash) initialization                                 */
 257 #define CONFIG_SYS_EBC_PB0AP            (EBC_BXAP_BME_DISABLED      |           \
 258                                  EBC_BXAP_TWT_ENCODE(7)     |           \
 259                                  EBC_BXAP_BCE_DISABLE       |           \
 260                                  EBC_BXAP_BCT_2TRANS        |           \
 261                                  EBC_BXAP_CSN_ENCODE(0)     |           \
 262                                  EBC_BXAP_OEN_ENCODE(0)     |           \
 263                                  EBC_BXAP_WBN_ENCODE(0)     |           \
 264                                  EBC_BXAP_WBF_ENCODE(0)     |           \
 265                                  EBC_BXAP_TH_ENCODE(0)      |           \
 266                                  EBC_BXAP_RE_DISABLED       |           \
 267                                  EBC_BXAP_SOR_DELAYED       |           \
 268                                  EBC_BXAP_BEM_WRITEONLY     |           \
 269                                  EBC_BXAP_PEN_DISABLED)
 270 #define CONFIG_SYS_EBC_PB0CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |   \
 271                                  EBC_BXCR_BS_16MB                    |  \
 272                                  EBC_BXCR_BU_RW                      |  \
 273                                  EBC_BXCR_BW_16BIT)
 274
 275 /* Memory Bank 1 (Xilinx System ACE controller) initialization          */
 276 #define CONFIG_SYS_EBC_PB1AP            (EBC_BXAP_BME_DISABLED      |           \
 277                                  EBC_BXAP_TWT_ENCODE(4)     |           \
 278                                  EBC_BXAP_BCE_DISABLE       |           \
 279                                  EBC_BXAP_BCT_2TRANS        |           \
 280                                  EBC_BXAP_CSN_ENCODE(0)     |           \
 281                                  EBC_BXAP_OEN_ENCODE(0)     |           \
 282                                  EBC_BXAP_WBN_ENCODE(0)     |           \
 283                                  EBC_BXAP_WBF_ENCODE(0)     |           \
 284                                  EBC_BXAP_TH_ENCODE(0)      |           \
 285                                  EBC_BXAP_RE_DISABLED       |           \
 286                                  EBC_BXAP_SOR_NONDELAYED    |           \
 287                                  EBC_BXAP_BEM_WRITEONLY     |           \
 288                                  EBC_BXAP_PEN_DISABLED)
 289 #define CONFIG_SYS_EBC_PB1CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |    \
 290                                  EBC_BXCR_BS_1MB                    |   \
 291                                  EBC_BXCR_BU_RW                     |   \
 292                                  EBC_BXCR_BW_16BIT)
 293
 294 /*-------------------------------------------------------------------------
 295  * Initialize EBC CONFIG -
 296  * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 297  * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 298  *-------------------------------------------------------------------------*/
 299 #define CONFIG_SYS_EBC_CFG              (EBC_CFG_LE_UNLOCK    | \
 300                                  EBC_CFG_PTD_ENABLE   | \
 301                                  EBC_CFG_RTC_16PERCLK | \
 302                                  EBC_CFG_ATC_PREVIOUS | \
 303                                  EBC_CFG_DTC_PREVIOUS | \
 304                                  EBC_CFG_CTC_PREVIOUS | \
 305                                  EBC_CFG_OEO_PREVIOUS | \
 306                                  EBC_CFG_EMC_DEFAULT  | \
 307                                  EBC_CFG_PME_DISABLE  | \
 308                                  EBC_CFG_PR_16)
 309
 310 /*-----------------------------------------------------------------------
 311  * GPIO Setup
 312  *----------------------------------------------------------------------*/
 313 #define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
 314 #define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
 315 #define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
 316 #define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
 317
 318 #define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
 319                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
 320                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
 321                                  GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
 322 #define CONFIG_SYS_GPIO_OR              GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 323 #define CONFIG_SYS_GPIO_TCR             GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 324 #define CONFIG_SYS_GPIO_ODR             0
 325
 326 #endif  /* __CONFIG_H */