include/configs/kilauea.h

   1 /*
   2  * Copyright (c) 2008 Nuovation System Designs, LLC
   3  *   Grant Erickson <gerickson@nuovations.com>
   4  *
   5  * (C) Copyright 2007
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /************************************************************************
  28  * kilauea.h - configuration for AMCC Kilauea (405EX)
  29  ***********************************************************************/
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*-----------------------------------------------------------------------
  35  * High Level Configuration Options
  36  *----------------------------------------------------------------------*/
  37 #define CONFIG_KILAUEA          1               /* Board is Kilauea     */
  38 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  39 #define CONFIG_405EX            1               /* Specifc 405EX support*/
  40 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  41
  42 /*
  43  * Include common defines/options for all AMCC eval boards
  44  */
  45 #define CONFIG_HOSTNAME         kilauea
  46 #include "amcc-common.h"
  47
  48 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  49 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  50 #define CONFIG_BOARD_EMAC_COUNT
  51
  52 /*-----------------------------------------------------------------------
  53  * Base addresses -- Note these are effective addresses where the
  54  * actual resources get mapped (not physical addresses)
  55  *----------------------------------------------------------------------*/
  56 #define CFG_FLASH_BASE          0xFC000000
  57 #define CFG_NAND_ADDR           0xF8000000
  58 #define CFG_FPGA_BASE           0xF0000000
  59 #define CFG_PERIPHERAL_BASE     0xEF600000      /* internal peripherals*/
  60
  61 /*-----------------------------------------------------------------------
  62  * Initial RAM & Stack Pointer Configuration Options
  63  *
  64  *   There are traditionally three options for the primordial
  65  *   (i.e. initial) stack usage on the 405-series:
  66  *
  67  *      1) On-chip Memory (OCM) (i.e. SRAM)
  68  *      2) Data cache
  69  *      3) SDRAM
  70  *
  71  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  72  *   the latter of which is less than desireable since it requires
  73  *   setting up the SDRAM and ECC in assembly code.
  74  *
  75  *   To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
  76  *   select on the External Bus Controller (EBC) and then select a
  77  *   value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
  78  *   physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
  79  *   select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
  80  *   physical SDRAM to use (3).
  81  *-----------------------------------------------------------------------*/
  82
  83 #define CFG_INIT_DCACHE_CS      4
  84
  85 #if defined(CFG_INIT_DCACHE_CS)
  86 #define CFG_INIT_RAM_ADDR       (CFG_SDRAM_BASE + ( 1 << 30))   /*  1 GiB */
  87 #else
  88 #define CFG_INIT_RAM_ADDR       (CFG_SDRAM_BASE + (32 << 20))   /* 32 MiB */
  89 #endif /* defined(CFG_INIT_DCACHE_CS) */
  90
  91 #define CFG_INIT_RAM_END        (4 << 10)                       /*  4 KiB */
  92 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data */
  93 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  94
  95 /*
  96  * If the data cache is being used for the primordial stack and global
  97  * data area, the POST word must be placed somewhere else. The General
  98  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
  99  * its compare and mask register contents across reset, so it is used
 100  * for the POST word.
 101  */
 102
 103 #if defined(CFG_INIT_DCACHE_CS)
 104 # define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
 105 # define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
 106 #else
 107 # define CFG_INIT_EXTRA_SIZE    16
 108 # define CFG_INIT_SP_OFFSET     (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
 109 # define CFG_POST_WORD_ADDR     (CFG_GBL_DATA_OFFSET - 4)
 110 # define CFG_OCM_DATA_ADDR      CFG_INIT_RAM_ADDR
 111 #endif /* defined(CFG_INIT_DCACHE_CS) */
 112
 113 /*-----------------------------------------------------------------------
 114  * Serial Port
 115  *----------------------------------------------------------------------*/
 116 #define CFG_EXT_SERIAL_CLOCK    11059200        /* ext. 11.059MHz clk   */
 117 /* define this if you want console on UART1 */
 118 #undef CONFIG_UART1_CONSOLE
 119
 120 /*-----------------------------------------------------------------------
 121  * Environment
 122  *----------------------------------------------------------------------*/
 123 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 124 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 125 #else
 126 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
 127 #define CFG_ENV_IS_EMBEDDED     1       /* use embedded environment */
 128 #endif
 129
 130 /*-----------------------------------------------------------------------
 131  * FLASH related
 132  *----------------------------------------------------------------------*/
 133 #define CFG_FLASH_CFI                   /* The flash is CFI compatible  */
 134 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 135
 136 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
 137 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 138 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 139
 140 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 141 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 142
 143 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 144 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 145
 146 #ifdef CFG_ENV_IS_IN_FLASH
 147 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector  */
 148 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 149 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 150
 151 /* Address and size of Redundant Environment Sector     */
 152 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 153 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 154 #endif /* CFG_ENV_IS_IN_FLASH */
 155
 156 /*
 157  * IPL (Initial Program Loader, integrated inside CPU)
 158  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 159  *
 160  * SPL (Secondary Program Loader)
 161  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 162  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 163  * controller and the NAND controller so that the special U-Boot image can be
 164  * loaded from NAND to SDRAM.
 165  *
 166  * NUB (NAND U-Boot)
 167  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 168  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 169  *
 170  * On 405EX the SPL is copied to SDRAM before the NAND controller is
 171  * set up. While still running from location 0xfffff000...0xffffffff the
 172  * NAND controller cannot be accessed since it is attached to CS0 too.
 173  */
 174 #define CFG_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location                 */
 175 #define CFG_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                     */
 176 #define CFG_NAND_BOOT_SPL_DST   0x00800000      /* Copy SPL here                */
 177 #define CFG_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr        */
 178 #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
 179 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 180
 181 /*
 182  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 183  */
 184 #define CFG_NAND_U_BOOT_OFFS    (16 << 10)      /* Offset to RAM U-Boot image   */
 185 #define CFG_NAND_U_BOOT_SIZE    (384 << 10)     /* Size of RAM U-Boot image     */
 186
 187 /*
 188  * Now the NAND chip has to be defined (no autodetection used!)
 189  */
 190 #define CFG_NAND_PAGE_SIZE      512             /* NAND chip page size          */
 191 #define CFG_NAND_BLOCK_SIZE     (16 << 10)      /* NAND chip block size         */
 192 #define CFG_NAND_PAGE_COUNT     32              /* NAND chip page count         */
 193 #define CFG_NAND_BAD_BLOCK_POS  5               /* Location of bad block marker */
 194 #define CFG_NAND_4_ADDR_CYCLE   1               /* Fourth addr used (>32MB)     */
 195
 196 #define CFG_NAND_ECCSIZE        256
 197 #define CFG_NAND_ECCBYTES       3
 198 #define CFG_NAND_ECCSTEPS       (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
 199 #define CFG_NAND_OOBSIZE        16
 200 #define CFG_NAND_ECCTOTAL       (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 201 #define CFG_NAND_ECCPOS         {0, 1, 2, 3, 6, 7}
 202
 203 #ifdef CONFIG_ENV_IS_IN_NAND
 204 /*
 205  * For NAND booting the environment is embedded in the U-Boot image. Please take
 206  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 207  */
 208 #define CFG_ENV_SIZE            CFG_NAND_BLOCK_SIZE
 209 #define CFG_ENV_OFFSET          (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
 210 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET + CFG_ENV_SIZE)
 211 #endif
 212
 213 /*-----------------------------------------------------------------------
 214  * NAND FLASH
 215  *----------------------------------------------------------------------*/
 216 #define CFG_MAX_NAND_DEVICE     1
 217 #define NAND_MAX_CHIPS          1
 218 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 219 #define CFG_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 220
 221 /*-----------------------------------------------------------------------
 222  * DDR SDRAM
 223  *----------------------------------------------------------------------*/
 224 #define CFG_MBYTES_SDRAM        (256)           /* 256MB                        */
 225
 226 /*
 227  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 228  *
 229  * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
 230  *       SDRAM Controller DDR autocalibration values and takes a lot longer
 231  *       to run than Method_B.
 232  * (See the Method_A and Method_B algorithm discription in the file:
 233  *      cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
 234  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
 235  *
 236  * DDR Autocalibration Method_B is the default.
 237  */
 238 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
 239 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 240 #undef  CONFIG_PPC4xx_DDR_METHOD_A
 241
 242 #define CFG_SDRAM0_MB0CF_BASE   ((  0 << 20) + CFG_SDRAM_BASE)
 243
 244 /* DDR1/2 SDRAM Device Control Register Data Values */
 245 #define CFG_SDRAM0_MB0CF        ((CFG_SDRAM0_MB0CF_BASE >> 3)   | \
 246                                  SDRAM_RXBAS_SDSZ_256MB         | \
 247                                  SDRAM_RXBAS_SDAM_MODE7         | \
 248                                  SDRAM_RXBAS_SDBE_ENABLE)
 249 #define CFG_SDRAM0_MB1CF        SDRAM_RXBAS_SDBE_DISABLE
 250 #define CFG_SDRAM0_MB2CF        SDRAM_RXBAS_SDBE_DISABLE
 251 #define CFG_SDRAM0_MB3CF        SDRAM_RXBAS_SDBE_DISABLE
 252 #define CFG_SDRAM0_MCOPT1       (SDRAM_MCOPT1_PMU_OPEN          | \
 253                                  SDRAM_MCOPT1_8_BANKS           | \
 254                                  SDRAM_MCOPT1_DDR2_TYPE         | \
 255                                  SDRAM_MCOPT1_QDEP              | \
 256                                  SDRAM_MCOPT1_DCOO_DISABLED)
 257 #define CFG_SDRAM0_MCOPT2       0x00000000
 258 #define CFG_SDRAM0_MODT0        (SDRAM_MODT_EB0W_ENABLE | \
 259                                  SDRAM_MODT_EB0R_ENABLE)
 260 #define CFG_SDRAM0_MODT1        0x00000000
 261 #define CFG_SDRAM0_CODT         (SDRAM_CODT_RK0R_ON             | \
 262                                  SDRAM_CODT_CKLZ_36OHM          | \
 263                                  SDRAM_CODT_DQS_1_8_V_DDR2      | \
 264                                  SDRAM_CODT_IO_NMODE)
 265 #define CFG_SDRAM0_RTR          SDRAM_RTR_RINT_ENCODE(1560)
 266 #define CFG_SDRAM0_INITPLR0     (SDRAM_INITPLR_ENABLE                   | \
 267                 SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
 268                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 269 #define CFG_SDRAM0_INITPLR1     (SDRAM_INITPLR_ENABLE                   | \
 270                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 271                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 272                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 273                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 274 #define CFG_SDRAM0_INITPLR2     (SDRAM_INITPLR_ENABLE                   | \
 275                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 276                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 277                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
 278                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 279 #define CFG_SDRAM0_INITPLR3     (SDRAM_INITPLR_ENABLE                   | \
 280                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 281                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 282                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
 283                 SDRAM_INITPLR_IMA_ENCODE(0))
 284 #define CFG_SDRAM0_INITPLR4     (SDRAM_INITPLR_ENABLE                   | \
 285                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 286                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 287                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 288                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 289                                          JEDEC_MA_EMR_RTT_75OHM))
 290 #define CFG_SDRAM0_INITPLR5     (SDRAM_INITPLR_ENABLE                   | \
 291                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 292                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 293                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 294                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 295                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 296                                          JEDEC_MA_MR_BLEN_4 | \
 297                                          JEDEC_MA_MR_DLL_RESET))
 298 #define CFG_SDRAM0_INITPLR6     (SDRAM_INITPLR_ENABLE                   | \
 299                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 300                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 301                 SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
 302                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 303 #define CFG_SDRAM0_INITPLR7     (SDRAM_INITPLR_ENABLE                   | \
 304                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 305                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 306 #define CFG_SDRAM0_INITPLR8     (SDRAM_INITPLR_ENABLE                   | \
 307                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 308                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 309 #define CFG_SDRAM0_INITPLR9     (SDRAM_INITPLR_ENABLE                   | \
 310                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 311                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 312 #define CFG_SDRAM0_INITPLR10    (SDRAM_INITPLR_ENABLE                   | \
 313                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 314                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 315 #define CFG_SDRAM0_INITPLR11    (SDRAM_INITPLR_ENABLE                   | \
 316                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 317                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 318                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 319                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 320                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 321                                          JEDEC_MA_MR_BLEN_4))
 322 #define CFG_SDRAM0_INITPLR12    (SDRAM_INITPLR_ENABLE                   | \
 323                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 324                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 325                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 326                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
 327                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 328                                          JEDEC_MA_EMR_DQS_DISABLE | \
 329                                          JEDEC_MA_EMR_RTT_DISABLED | \
 330                                          JEDEC_MA_EMR_ODS_NORMAL))
 331 #define CFG_SDRAM0_INITPLR13    (SDRAM_INITPLR_ENABLE                   | \
 332                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 333                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 334                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 335                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
 336                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 337                                          JEDEC_MA_EMR_DQS_DISABLE | \
 338                                          JEDEC_MA_EMR_RTT_DISABLED | \
 339                                          JEDEC_MA_EMR_ODS_NORMAL))
 340 #define CFG_SDRAM0_INITPLR14    (SDRAM_INITPLR_DISABLE)
 341 #define CFG_SDRAM0_INITPLR15    (SDRAM_INITPLR_DISABLE)
 342 #define CFG_SDRAM0_RQDC         (SDRAM_RQDC_RQDE_ENABLE | \
 343                                  SDRAM_RQDC_RQFD_ENCODE(56))
 344 #define CFG_SDRAM0_RFDC         SDRAM_RFDC_RFFD_ENCODE(521)
 345 #define CFG_SDRAM0_RDCC         (SDRAM_RDCC_RDSS_T2)
 346 #define CFG_SDRAM0_DLCR         (SDRAM_DLCR_DCLM_AUTO           | \
 347                                  SDRAM_DLCR_DLCS_CONT_DONE      | \
 348                                  SDRAM_DLCR_DLCV_ENCODE(165))
 349 #define CFG_SDRAM0_CLKTR        (SDRAM_CLKTR_CLKP_180_DEG_ADV)
 350 #define CFG_SDRAM0_WRDTR        0x00000000
 351 #define CFG_SDRAM0_SDTR1        (SDRAM_SDTR1_LDOF_2_CLK | \
 352                                  SDRAM_SDTR1_RTW_2_CLK  | \
 353                                  SDRAM_SDTR1_RTRO_1_CLK)
 354 #define CFG_SDRAM0_SDTR2        (SDRAM_SDTR2_RCD_3_CLK          | \
 355                                  SDRAM_SDTR2_WTR_2_CLK          | \
 356                                  SDRAM_SDTR2_XSNR_32_CLK        | \
 357                                  SDRAM_SDTR2_WPC_4_CLK          | \
 358                                  SDRAM_SDTR2_RPC_2_CLK          | \
 359                                  SDRAM_SDTR2_RP_3_CLK           | \
 360                                  SDRAM_SDTR2_RRD_2_CLK)
 361 #define CFG_SDRAM0_SDTR3        (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 362                                  SDRAM_SDTR3_RC_ENCODE(11)      | \
 363                                  SDRAM_SDTR3_XCS                | \
 364                                  SDRAM_SDTR3_RFC_ENCODE(26))
 365 #define CFG_SDRAM0_MMODE        (SDRAM_MMODE_WR_DDR2_3_CYC | \
 366                                  SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
 367                                  SDRAM_MMODE_BLEN_4)
 368 #define CFG_SDRAM0_MEMODE       (SDRAM_MEMODE_DQS_DISABLE | \
 369                                  SDRAM_MEMODE_RTT_75OHM)
 370
 371 /*-----------------------------------------------------------------------
 372  * I2C
 373  *----------------------------------------------------------------------*/
 374 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 375
 376 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  6       /* 24C02 requires 5ms delay */
 377 #define CFG_I2C_EEPROM_ADDR     0x52    /* I2C boot EEPROM (24C02BN)    */
 378 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 379
 380 /* Standard DTT sensor configuration */
 381 #define CONFIG_DTT_DS1775       1
 382 #define CONFIG_DTT_SENSORS      { 0 }
 383 #define CFG_I2C_DTT_ADDR        0x48
 384
 385 /* RTC configuration */
 386 #define CONFIG_RTC_DS1338       1
 387 #define CFG_I2C_RTC_ADDR        0x68
 388
 389 /*-----------------------------------------------------------------------
 390  * Ethernet
 391  *----------------------------------------------------------------------*/
 392 #define CONFIG_M88E1111_PHY     1
 393 #define CONFIG_IBM_EMAC4_V4     1
 394 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 395 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 396
 397 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 398 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 399
 400 #define CONFIG_HAS_ETH0         1
 401
 402 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 403 #define CONFIG_PHY1_ADDR        2
 404
 405 /* Debug messages for the DDR autocalibration */
 406 #define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
 407
 408 /*
 409  * Default environment variables
 410  */
 411 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 412         CONFIG_AMCC_DEF_ENV                                             \
 413         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 414         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 415         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 416         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 417         "logversion=2\0"                                                \
 418         "kernel_addr=fc000000\0"                                        \
 419         "fdt_addr=fc1e0000\0"                                           \
 420         "ramdisk_addr=fc200000\0"                                       \
 421         "pciconfighost=1\0"                                             \
 422         "pcie_mode=RP:RP\0"                                             \
 423         ""
 424
 425 /*
 426  * Commands additional to the ones defined in amcc-common.h
 427  */
 428 #define CONFIG_CMD_DATE
 429 #define CONFIG_CMD_LOG
 430 #define CONFIG_CMD_NAND
 431 #define CONFIG_CMD_PCI
 432 #define CONFIG_CMD_SNTP
 433
 434 /* POST support */
 435 #define CONFIG_POST             (CFG_POST_CACHE         | \
 436                                  CFG_POST_CPU           | \
 437                                  CFG_POST_ETHER         | \
 438                                  CFG_POST_I2C           | \
 439                                  CFG_POST_MEMORY        | \
 440                                  CFG_POST_UART)
 441
 442 /* Define here the base-addresses of the UARTs to test in POST */
 443 #define CFG_POST_UART_TABLE     {UART0_BASE, UART1_BASE}
 444
 445 #define CONFIG_LOGBUFFER
 446 #define CFG_POST_CACHE_ADDR     0x00800000 /* free virtual address      */
 447
 448 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 449
 450 /*-----------------------------------------------------------------------
 451  * PCI stuff
 452  *----------------------------------------------------------------------*/
 453 #define CONFIG_PCI                      /* include pci support          */
 454 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 455 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 456 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 457
 458 /*-----------------------------------------------------------------------
 459  * PCIe stuff
 460  *----------------------------------------------------------------------*/
 461 #define CFG_PCIE_MEMBASE        0x90000000      /* mapped PCIe memory   */
 462 #define CFG_PCIE_MEMSIZE        0x08000000      /* 128 Meg, smallest incr per port */
 463
 464 #define CFG_PCIE0_CFGBASE       0xa0000000      /* remote access */
 465 #define CFG_PCIE0_XCFGBASE      0xb0000000      /* local access */
 466 #define CFG_PCIE0_CFGMASK       0xe0000001      /* 512 Meg */
 467
 468 #define CFG_PCIE1_CFGBASE       0xc0000000      /* remote access */
 469 #define CFG_PCIE1_XCFGBASE      0xd0000000      /* local access */
 470 #define CFG_PCIE1_CFGMASK       0xe0000001      /* 512 Meg */
 471
 472 #define CFG_PCIE0_UTLBASE       0xef502000
 473 #define CFG_PCIE1_UTLBASE       0xef503000
 474
 475 /* base address of inbound PCIe window */
 476 #define CFG_PCIE_INBOUND_BASE   0x0000000000000000ULL
 477
 478 /*-----------------------------------------------------------------------
 479  * External Bus Controller (EBC) Setup
 480  *----------------------------------------------------------------------*/
 481 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 482 /* booting from NAND, so NAND chips select has to be on CS 0 */
 483 #define CFG_NAND_CS             0               /* NAND chip connected to CSx   */
 484
 485 /* Memory Bank 1 (NOR-FLASH) initialization                                     */
 486 #define CFG_EBC_PB1AP           0x05806500
 487 #define CFG_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 488
 489 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 490 #define CFG_EBC_PB0AP           0x018003c0
 491 #define CFG_EBC_PB0CR           (CFG_NAND_ADDR | 0x1e000)
 492 #else
 493 #define CFG_NAND_CS             1               /* NAND chip connected to CSx   */
 494
 495 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 496 #define CFG_EBC_PB0AP           0x05806500
 497 #define CFG_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 498
 499 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
 500 #define CFG_EBC_PB1AP           0x018003c0
 501 #define CFG_EBC_PB1CR           (CFG_NAND_ADDR | 0x1e000)
 502 #endif
 503
 504 /* Memory Bank 2 (FPGA) initialization                                          */
 505 #define CFG_EBC_PB2AP           0x9400C800
 506 #define CFG_EBC_PB2CR           (CFG_FPGA_BASE | 0x18000)
 507
 508 #define CFG_EBC_CFG             0x7FC00000 /*  EBC0_CFG */
 509
 510 /*-----------------------------------------------------------------------
 511  * GPIO Setup
 512  *----------------------------------------------------------------------*/
 513 #define CFG_4xx_GPIO_TABLE { /*   Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 514 {                                                                                       \
 515 /* GPIO Core 0 */                                                                       \
 516 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 517 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 518 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 519 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 520 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 521 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 522 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 523 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 524 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 525 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 526 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 527 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 528 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 529 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 530 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 531 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 532 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 533 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 534 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 535 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 536 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 537 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 538 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 539 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 540 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 541 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 542 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 543 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 544 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
 545 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 546 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 547 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 548 }                                                                                               \
 549 }
 550
 551 /*-----------------------------------------------------------------------
 552  * Some Kilauea stuff..., mainly fpga registers
 553  */
 554 #define CFG_FPGA_REG_BASE               CFG_FPGA_BASE
 555 #define CFG_FPGA_FIFO_BASE              (in32(CFG_FPGA_BASE) | (1 << 10))
 556
 557 /* interrupt */
 558 #define CFG_FPGA_SLIC0_R_DPRAM_INT      0x80000000
 559 #define CFG_FPGA_SLIC0_W_DPRAM_INT      0x40000000
 560 #define CFG_FPGA_SLIC1_R_DPRAM_INT      0x20000000
 561 #define CFG_FPGA_SLIC1_W_DPRAM_INT      0x10000000
 562 #define CFG_FPGA_PHY0_INT               0x08000000
 563 #define CFG_FPGA_PHY1_INT               0x04000000
 564 #define CFG_FPGA_SLIC0_INT              0x02000000
 565 #define CFG_FPGA_SLIC1_INT              0x01000000
 566
 567 /* DPRAM setting */
 568 /* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
 569 #define CFG_FPGA_DPRAM_R_INT_LINE       0x00400000      /* 64 B */
 570 #define CFG_FPGA_DPRAM_W_INT_LINE       0x00100000      /* 64 B */
 571 #define CFG_FPGA_DPRAM_RW_TYPE          0x00080000
 572 #define CFG_FPGA_DPRAM_RST              0x00040000
 573 #define CFG_FPGA_UART0_FO               0x00020000
 574 #define CFG_FPGA_UART1_FO               0x00010000
 575
 576 /* loopback */
 577 #define CFG_FPGA_CHIPSIDE_LOOPBACK      0x00004000
 578 #define CFG_FPGA_LINESIDE_LOOPBACK      0x00008000
 579 #define CFG_FPGA_SLIC0_ENABLE           0x00002000
 580 #define CFG_FPGA_SLIC1_ENABLE           0x00001000
 581 #define CFG_FPGA_SLIC0_CS               0x00000800
 582 #define CFG_FPGA_SLIC1_CS               0x00000400
 583 #define CFG_FPGA_USER_LED0              0x00000200
 584 #define CFG_FPGA_USER_LED1              0x00000100
 585
 586 #endif  /* __CONFIG_H */