include/configs/kilauea.h

   1 /*
   2  * Copyright (c) 2008 Nuovation System Designs, LLC
   3  *   Grant Erickson <gerickson@nuovations.com>
   4  *
   5  * (C) Copyright 2007
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /************************************************************************
  12  * kilauea.h - configuration for AMCC Kilauea (405EX)
  13  ***********************************************************************/
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*-----------------------------------------------------------------------
  19  * High Level Configuration Options
  20  *----------------------------------------------------------------------*/
  21 #define CONFIG_KILAUEA          1               /* Board is Kilauea     */
  22 #define CONFIG_405EX            1               /* Specifc 405EX support*/
  23 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  24
  25 #ifndef CONFIG_SYS_TEXT_BASE
  26 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  27 #endif
  28
  29 /*
  30  * CHIP_21 errata - you must set this to match your exact CPU, else your
  31  * board will not boot.  DO NOT enable this unless you have JTAG available
  32  * for recovery, in the event you get it wrong.
  33  *
  34  * Kilauea uses the 405EX, while Haleakala uses the 405EXr.  Either board
  35  * may be equipped for security or not.  You must look at the CPU part
  36  * number to be sure what you have.
  37  */
  38 /* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
  39 /* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
  40 /* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
  41 /* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
  42
  43 /*
  44  * Include common defines/options for all AMCC eval boards
  45  */
  46 #define CONFIG_HOSTNAME         kilauea
  47 #include "amcc-common.h"
  48
  49 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  50 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  51 #define CONFIG_BOARD_TYPES
  52 #define CONFIG_BOARD_EMAC_COUNT
  53
  54 /*-----------------------------------------------------------------------
  55  * Base addresses -- Note these are effective addresses where the
  56  * actual resources get mapped (not physical addresses)
  57  *----------------------------------------------------------------------*/
  58 #define CONFIG_SYS_FLASH_BASE           0xFC000000
  59 #define CONFIG_SYS_NAND_ADDR            0xF8000000
  60 #define CONFIG_SYS_FPGA_BASE            0xF0000000
  61
  62 /*-----------------------------------------------------------------------
  63  * Initial RAM & Stack Pointer Configuration Options
  64  *
  65  *   There are traditionally three options for the primordial
  66  *   (i.e. initial) stack usage on the 405-series:
  67  *
  68  *      1) On-chip Memory (OCM) (i.e. SRAM)
  69  *      2) Data cache
  70  *      3) SDRAM
  71  *
  72  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  73  *   the latter of which is less than desireable since it requires
  74  *   setting up the SDRAM and ECC in assembly code.
  75  *
  76  *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  77  *   select on the External Bus Controller (EBC) and then select a
  78  *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  79  *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  80  *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  81  *   physical SDRAM to use (3).
  82  *-----------------------------------------------------------------------*/
  83
  84 #define CONFIG_SYS_INIT_DCACHE_CS       4
  85
  86 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
  87 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
  88 #else
  89 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
  90 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  91
  92 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)                       /*  4 KiB */
  93 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  94
  95 /*
  96  * If the data cache is being used for the primordial stack and global
  97  * data area, the POST word must be placed somewhere else. The General
  98  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
  99  * its compare and mask register contents across reset, so it is used
 100  * for the POST word.
 101  */
 102
 103 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
 104 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 105 # define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 106 #else
 107 # define CONFIG_SYS_INIT_EXTRA_SIZE     16
 108 # define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
 109 # define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
 110 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 111
 112 /*-----------------------------------------------------------------------
 113  * Serial Port
 114  *----------------------------------------------------------------------*/
 115 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
 116 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 117
 118 /*-----------------------------------------------------------------------
 119  * Environment
 120  *----------------------------------------------------------------------*/
 121 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 122 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 123 #else
 124 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
 125 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 126 #endif
 127
 128 /*-----------------------------------------------------------------------
 129  * FLASH related
 130  *----------------------------------------------------------------------*/
 131 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 132 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 133
 134 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 135 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 136 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 137
 138 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 139 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 140
 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 142 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 143
 144 #ifdef CONFIG_ENV_IS_IN_FLASH
 145 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 146 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 147 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 148
 149 /* Address and size of Redundant Environment Sector     */
 150 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 151 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 152 #endif /* CONFIG_ENV_IS_IN_FLASH */
 153
 154 /*
 155  * IPL (Initial Program Loader, integrated inside CPU)
 156  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 157  *
 158  * SPL (Secondary Program Loader)
 159  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 160  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 161  * controller and the NAND controller so that the special U-Boot image can be
 162  * loaded from NAND to SDRAM.
 163  *
 164  * NUB (NAND U-Boot)
 165  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 166  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 167  *
 168  * On 405EX the SPL is copied to SDRAM before the NAND controller is
 169  * set up. While still running from location 0xfffff000...0xffffffff the
 170  * NAND controller cannot be accessed since it is attached to CS0 too.
 171  */
 172 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 173 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 174 #define CONFIG_SYS_NAND_BOOT_SPL_DST    0x00800000      /* Copy SPL here                */
 175 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 176 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
 177 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 178
 179 /*
 180  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 181  */
 182 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 183 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 184
 185 /*
 186  * Now the NAND chip has to be defined (no autodetection used!)
 187  */
 188 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
 189 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
 190 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
 191 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
 192 #define CONFIG_SYS_NAND_4_ADDR_CYCLE    1               /* Fourth addr used (>32MB)     */
 193
 194 #define CONFIG_SYS_NAND_ECCSIZE 256
 195 #define CONFIG_SYS_NAND_ECCBYTES        3
 196 #define CONFIG_SYS_NAND_OOBSIZE 16
 197 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 198
 199 #ifdef CONFIG_ENV_IS_IN_NAND
 200 /*
 201  * For NAND booting the environment is embedded in the U-Boot image. Please take
 202  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 203  */
 204 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 205 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 206 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 207 #endif
 208
 209 /*-----------------------------------------------------------------------
 210  * NAND FLASH
 211  *----------------------------------------------------------------------*/
 212 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 213 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 214 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 215
 216 /*-----------------------------------------------------------------------
 217  * DDR SDRAM
 218  *----------------------------------------------------------------------*/
 219 #define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
 220
 221 /*
 222  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 223  *
 224  * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
 225  *       SDRAM Controller DDR autocalibration values and takes a lot longer
 226  *       to run than Method_B.
 227  * (See the Method_A and Method_B algorithm discription in the file:
 228  *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
 229  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
 230  *
 231  * DDR Autocalibration Method_B is the default.
 232  */
 233 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 234 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
 235 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 236 #undef  CONFIG_PPC4xx_DDR_METHOD_A
 237 #endif
 238
 239 #define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 240
 241 /* DDR1/2 SDRAM Device Control Register Data Values */
 242 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
 243                                  SDRAM_RXBAS_SDSZ_256MB         | \
 244                                  SDRAM_RXBAS_SDAM_MODE7         | \
 245                                  SDRAM_RXBAS_SDBE_ENABLE)
 246 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
 247 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
 248 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
 249 #define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN          | \
 250                                  SDRAM_MCOPT1_8_BANKS           | \
 251                                  SDRAM_MCOPT1_DDR2_TYPE         | \
 252                                  SDRAM_MCOPT1_QDEP              | \
 253                                  SDRAM_MCOPT1_DCOO_DISABLED)
 254 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 255 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
 256                                  SDRAM_MODT_EB0R_ENABLE)
 257 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
 258 #define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
 259                                  SDRAM_CODT_CKLZ_36OHM          | \
 260                                  SDRAM_CODT_DQS_1_8_V_DDR2      | \
 261                                  SDRAM_CODT_IO_NMODE)
 262 #define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 263 #define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE                   | \
 264                 SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
 265                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 266 #define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE                   | \
 267                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 268                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 269                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 270                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 271 #define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE                   | \
 272                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 273                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 274                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
 275                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 276 #define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE                   | \
 277                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 278                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 279                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
 280                 SDRAM_INITPLR_IMA_ENCODE(0))
 281 #define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE                   | \
 282                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 283                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 284                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 285                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 286                                          JEDEC_MA_EMR_RTT_75OHM))
 287 #define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE                   | \
 288                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 289                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 290                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 291                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 292                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 293                                          JEDEC_MA_MR_BLEN_4 | \
 294                                          JEDEC_MA_MR_DLL_RESET))
 295 #define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE                   | \
 296                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 297                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 298                 SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
 299                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 300 #define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE                   | \
 301                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 302                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 303 #define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE                   | \
 304                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 305                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 306 #define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE                   | \
 307                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 308                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 309 #define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE                   | \
 310                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 311                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 312 #define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE                   | \
 313                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 314                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 315                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 316                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 317                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 318                                          JEDEC_MA_MR_BLEN_4))
 319 #define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE                   | \
 320                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 321                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 322                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 323                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
 324                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 325                                          JEDEC_MA_EMR_DQS_DISABLE | \
 326                                          JEDEC_MA_EMR_RTT_DISABLED | \
 327                                          JEDEC_MA_EMR_ODS_NORMAL))
 328 #define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE                   | \
 329                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 330                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 331                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 332                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
 333                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 334                                          JEDEC_MA_EMR_DQS_DISABLE | \
 335                                          JEDEC_MA_EMR_RTT_DISABLED | \
 336                                          JEDEC_MA_EMR_ODS_NORMAL))
 337 #define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
 338 #define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
 339 #define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
 340                                  SDRAM_RQDC_RQFD_ENCODE(56))
 341 #define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
 342 #define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 343 #define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
 344                                  SDRAM_DLCR_DLCS_CONT_DONE      | \
 345                                  SDRAM_DLCR_DLCV_ENCODE(165))
 346 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
 347 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
 348 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
 349                                  SDRAM_SDTR1_RTW_2_CLK  | \
 350                                  SDRAM_SDTR1_RTRO_1_CLK)
 351 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK          | \
 352                                  SDRAM_SDTR2_WTR_2_CLK          | \
 353                                  SDRAM_SDTR2_XSNR_32_CLK        | \
 354                                  SDRAM_SDTR2_WPC_4_CLK          | \
 355                                  SDRAM_SDTR2_RPC_2_CLK          | \
 356                                  SDRAM_SDTR2_RP_3_CLK           | \
 357                                  SDRAM_SDTR2_RRD_2_CLK)
 358 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 359                                  SDRAM_SDTR3_RC_ENCODE(11)      | \
 360                                  SDRAM_SDTR3_XCS                | \
 361                                  SDRAM_SDTR3_RFC_ENCODE(26))
 362 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
 363                                  SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
 364                                  SDRAM_MMODE_BLEN_4)
 365 #define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
 366                                  SDRAM_MEMODE_RTT_75OHM)
 367
 368 /*-----------------------------------------------------------------------
 369  * I2C
 370  *----------------------------------------------------------------------*/
 371 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 372
 373 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
 374 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 375 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 376 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 377
 378 /* I2C bootstrap EEPROM */
 379 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 380 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 381 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 382
 383 /* Standard DTT sensor configuration */
 384 #define CONFIG_DTT_DS1775       1
 385 #define CONFIG_DTT_SENSORS      { 0 }
 386 #define CONFIG_SYS_I2C_DTT_ADDR 0x48
 387
 388 /* RTC configuration */
 389 #define CONFIG_RTC_DS1338       1
 390 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 391
 392 /*-----------------------------------------------------------------------
 393  * Ethernet
 394  *----------------------------------------------------------------------*/
 395 #define CONFIG_M88E1111_PHY     1
 396 #define CONFIG_IBM_EMAC4_V4     1
 397 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 398 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 399
 400 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 401 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 402
 403 #define CONFIG_HAS_ETH0         1
 404
 405 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 406 #define CONFIG_PHY1_ADDR        2
 407
 408 /* Debug messages for the DDR autocalibration */
 409 #define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
 410
 411 /*
 412  * Default environment variables
 413  */
 414 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 415         CONFIG_AMCC_DEF_ENV                                             \
 416         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 417         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 418         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 419         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 420         "logversion=2\0"                                                \
 421         "kernel_addr=fc000000\0"                                        \
 422         "fdt_addr=fc1e0000\0"                                           \
 423         "ramdisk_addr=fc200000\0"                                       \
 424         "pciconfighost=1\0"                                             \
 425         "pcie_mode=RP:RP\0"                                             \
 426         ""
 427
 428 /*
 429  * Commands additional to the ones defined in amcc-common.h
 430  */
 431 #define CONFIG_CMD_CHIP_CONFIG
 432 #define CONFIG_CMD_DATE
 433 #define CONFIG_CMD_NAND
 434 #define CONFIG_CMD_PCI
 435 #define CONFIG_CMD_SNTP
 436
 437 /*
 438  * Don't run the memory POST on the NAND-booting version. It will
 439  * overwrite part of the U-Boot image which is already loaded from NAND
 440  * to SDRAM.
 441  */
 442 #if defined(CONFIG_NAND_U_BOOT)
 443 #define CONFIG_SYS_POST_MEMORY_ON       0
 444 #else
 445 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 446 #endif
 447
 448 /* POST support */
 449 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 450                                  CONFIG_SYS_POST_CPU            | \
 451                                  CONFIG_SYS_POST_ETHER          | \
 452                                  CONFIG_SYS_POST_I2C            | \
 453                                  CONFIG_SYS_POST_MEMORY_ON      | \
 454                                  CONFIG_SYS_POST_UART)
 455
 456 /* Define here the base-addresses of the UARTs to test in POST */
 457 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 458                         CONFIG_SYS_NS16550_COM2 }
 459
 460 #define CONFIG_LOGBUFFER
 461 #define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
 462
 463 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 464
 465 /*-----------------------------------------------------------------------
 466  * PCI stuff
 467  *----------------------------------------------------------------------*/
 468 #define CONFIG_PCI                      /* include pci support          */
 469 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 470 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 471 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 472 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 473
 474 /*-----------------------------------------------------------------------
 475  * PCIe stuff
 476  *----------------------------------------------------------------------*/
 477 #define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
 478 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
 479
 480 #define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
 481 #define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
 482 #define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
 483
 484 #define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
 485 #define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
 486 #define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
 487
 488 #define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
 489 #define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
 490
 491 /* base address of inbound PCIe window */
 492 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
 493
 494 /*-----------------------------------------------------------------------
 495  * External Bus Controller (EBC) Setup
 496  *----------------------------------------------------------------------*/
 497 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 498 /* booting from NAND, so NAND chips select has to be on CS 0 */
 499 #define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
 500
 501 /* Memory Bank 1 (NOR-FLASH) initialization                                     */
 502 #define CONFIG_SYS_EBC_PB1AP            0x05806500
 503 #define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 504
 505 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 506 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 507 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 508 #else
 509 #define CONFIG_SYS_NAND_CS              1               /* NAND chip connected to CSx   */
 510
 511 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 512 #define CONFIG_SYS_EBC_PB0AP            0x05806500
 513 #define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 514
 515 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
 516 #define CONFIG_SYS_EBC_PB1AP            0x018003c0
 517 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 518 #endif
 519
 520 /* Memory Bank 2 (FPGA) initialization                                  */
 521 #define CONFIG_SYS_EBC_PB2AP            (EBC_BXAP_BME_ENABLED |         \
 522                                          EBC_BXAP_FWT_ENCODE(6) |       \
 523                                          EBC_BXAP_BWT_ENCODE(1) |       \
 524                                          EBC_BXAP_BCE_DISABLE |         \
 525                                          EBC_BXAP_BCT_2TRANS |          \
 526                                          EBC_BXAP_CSN_ENCODE(0) |       \
 527                                          EBC_BXAP_OEN_ENCODE(0) |       \
 528                                          EBC_BXAP_WBN_ENCODE(3) |       \
 529                                          EBC_BXAP_WBF_ENCODE(1) |       \
 530                                          EBC_BXAP_TH_ENCODE(4) |        \
 531                                          EBC_BXAP_RE_DISABLED |         \
 532                                          EBC_BXAP_SOR_DELAYED |         \
 533                                          EBC_BXAP_BEM_WRITEONLY |       \
 534                                          EBC_BXAP_PEN_DISABLED)
 535 #define CONFIG_SYS_EBC_PB2CR    (CONFIG_SYS_FPGA_BASE | 0x18000)
 536
 537 #define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
 538
 539 /*-----------------------------------------------------------------------
 540  * GPIO Setup
 541  *----------------------------------------------------------------------*/
 542 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 543 {                                                                                       \
 544 /* GPIO Core 0 */                                                                       \
 545 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 546 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 547 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 548 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 549 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 550 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 551 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 552 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 553 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 554 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 555 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 556 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 557 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 558 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 559 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 560 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 561 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 562 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 563 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 564 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 565 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 566 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 567 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 568 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 569 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 570 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 571 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 572 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 573 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
 574 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 575 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 576 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 577 }                                                                                               \
 578 }
 579
 580 /*-----------------------------------------------------------------------
 581  * Some Kilauea stuff..., mainly fpga registers
 582  */
 583 #define CONFIG_SYS_FPGA_REG_BASE                CONFIG_SYS_FPGA_BASE
 584 #define CONFIG_SYS_FPGA_FIFO_BASE               (CONFIG_SYS_FPGA_BASE | (1 << 10))
 585
 586 /* interrupt */
 587 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT       0x80000000
 588 #define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT       0x40000000
 589 #define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT       0x20000000
 590 #define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT       0x10000000
 591 #define CONFIG_SYS_FPGA_PHY0_INT                0x08000000
 592 #define CONFIG_SYS_FPGA_PHY1_INT                0x04000000
 593 #define CONFIG_SYS_FPGA_SLIC0_INT               0x02000000
 594 #define CONFIG_SYS_FPGA_SLIC1_INT               0x01000000
 595
 596 /* DPRAM setting */
 597 /* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
 598 #define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE        0x00400000      /* 64 B */
 599 #define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE        0x00100000      /* 64 B */
 600 #define CONFIG_SYS_FPGA_DPRAM_RW_TYPE           0x00080000
 601 #define CONFIG_SYS_FPGA_DPRAM_RST               0x00040000
 602 #define CONFIG_SYS_FPGA_UART0_FO                0x00020000
 603 #define CONFIG_SYS_FPGA_UART1_FO                0x00010000
 604
 605 /* loopback */
 606 #define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK       0x00004000
 607 #define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK       0x00008000
 608 #define CONFIG_SYS_FPGA_SLIC0_ENABLE            0x00002000
 609 #define CONFIG_SYS_FPGA_SLIC1_ENABLE            0x00001000
 610 #define CONFIG_SYS_FPGA_SLIC0_CS                0x00000800
 611 #define CONFIG_SYS_FPGA_SLIC1_CS                0x00000400
 612 #define CONFIG_SYS_FPGA_USER_LED0               0x00000200
 613 #define CONFIG_SYS_FPGA_USER_LED1               0x00000100
 614
 615 #define CONFIG_SYS_FPGA_MAGIC_MASK              0xffff0000
 616 #define CONFIG_SYS_FPGA_MAGIC                   0xabcd0000
 617 #define CONFIG_SYS_FPGA_VER_MASK                0x0000ff00
 618
 619 #endif  /* __CONFIG_H */