include/configs/kilauea.h

   1 /*
   2  * Copyright (c) 2008 Nuovation System Designs, LLC
   3  *   Grant Erickson <gerickson@nuovations.com>
   4  *
   5  * (C) Copyright 2007
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /************************************************************************
  12  * kilauea.h - configuration for AMCC Kilauea (405EX)
  13  ***********************************************************************/
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*-----------------------------------------------------------------------
  19  * High Level Configuration Options
  20  *----------------------------------------------------------------------*/
  21 #define CONFIG_KILAUEA          1               /* Board is Kilauea     */
  22 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  23 #define CONFIG_405EX            1               /* Specifc 405EX support*/
  24 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  25
  26 #ifndef CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  28 #endif
  29
  30 /*
  31  * CHIP_21 errata - you must set this to match your exact CPU, else your
  32  * board will not boot.  DO NOT enable this unless you have JTAG available
  33  * for recovery, in the event you get it wrong.
  34  *
  35  * Kilauea uses the 405EX, while Haleakala uses the 405EXr.  Either board
  36  * may be equipped for security or not.  You must look at the CPU part
  37  * number to be sure what you have.
  38  */
  39 /* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
  40 /* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
  41 /* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
  42 /* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
  43
  44 /*
  45  * Include common defines/options for all AMCC eval boards
  46  */
  47 #define CONFIG_HOSTNAME         kilauea
  48 #include "amcc-common.h"
  49
  50 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  51 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  52 #define CONFIG_BOARD_TYPES
  53 #define CONFIG_BOARD_EMAC_COUNT
  54
  55 /*-----------------------------------------------------------------------
  56  * Base addresses -- Note these are effective addresses where the
  57  * actual resources get mapped (not physical addresses)
  58  *----------------------------------------------------------------------*/
  59 #define CONFIG_SYS_FLASH_BASE           0xFC000000
  60 #define CONFIG_SYS_NAND_ADDR            0xF8000000
  61 #define CONFIG_SYS_FPGA_BASE            0xF0000000
  62
  63 /*-----------------------------------------------------------------------
  64  * Initial RAM & Stack Pointer Configuration Options
  65  *
  66  *   There are traditionally three options for the primordial
  67  *   (i.e. initial) stack usage on the 405-series:
  68  *
  69  *      1) On-chip Memory (OCM) (i.e. SRAM)
  70  *      2) Data cache
  71  *      3) SDRAM
  72  *
  73  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  74  *   the latter of which is less than desireable since it requires
  75  *   setting up the SDRAM and ECC in assembly code.
  76  *
  77  *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  78  *   select on the External Bus Controller (EBC) and then select a
  79  *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  80  *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  81  *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  82  *   physical SDRAM to use (3).
  83  *-----------------------------------------------------------------------*/
  84
  85 #define CONFIG_SYS_INIT_DCACHE_CS       4
  86
  87 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
  88 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
  89 #else
  90 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
  91 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  92
  93 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)                       /*  4 KiB */
  94 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  95
  96 /*
  97  * If the data cache is being used for the primordial stack and global
  98  * data area, the POST word must be placed somewhere else. The General
  99  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
 100  * its compare and mask register contents across reset, so it is used
 101  * for the POST word.
 102  */
 103
 104 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
 105 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 106 # define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 107 #else
 108 # define CONFIG_SYS_INIT_EXTRA_SIZE     16
 109 # define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
 110 # define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
 111 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 112
 113 /*-----------------------------------------------------------------------
 114  * Serial Port
 115  *----------------------------------------------------------------------*/
 116 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
 117 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 118
 119 /*-----------------------------------------------------------------------
 120  * Environment
 121  *----------------------------------------------------------------------*/
 122 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 123 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 124 #else
 125 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
 126 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 127 #endif
 128
 129 /*-----------------------------------------------------------------------
 130  * FLASH related
 131  *----------------------------------------------------------------------*/
 132 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 133 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 134
 135 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 136 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 137 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 138
 139 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 140 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 141
 142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 143 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 144
 145 #ifdef CONFIG_ENV_IS_IN_FLASH
 146 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 147 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 148 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 149
 150 /* Address and size of Redundant Environment Sector     */
 151 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 152 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 153 #endif /* CONFIG_ENV_IS_IN_FLASH */
 154
 155 /*
 156  * IPL (Initial Program Loader, integrated inside CPU)
 157  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 158  *
 159  * SPL (Secondary Program Loader)
 160  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 161  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 162  * controller and the NAND controller so that the special U-Boot image can be
 163  * loaded from NAND to SDRAM.
 164  *
 165  * NUB (NAND U-Boot)
 166  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 167  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 168  *
 169  * On 405EX the SPL is copied to SDRAM before the NAND controller is
 170  * set up. While still running from location 0xfffff000...0xffffffff the
 171  * NAND controller cannot be accessed since it is attached to CS0 too.
 172  */
 173 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 174 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 175 #define CONFIG_SYS_NAND_BOOT_SPL_DST    0x00800000      /* Copy SPL here                */
 176 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 177 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
 178 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 179
 180 /*
 181  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 182  */
 183 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 184 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 185
 186 /*
 187  * Now the NAND chip has to be defined (no autodetection used!)
 188  */
 189 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
 190 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
 191 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
 192 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
 193 #define CONFIG_SYS_NAND_4_ADDR_CYCLE    1               /* Fourth addr used (>32MB)     */
 194
 195 #define CONFIG_SYS_NAND_ECCSIZE 256
 196 #define CONFIG_SYS_NAND_ECCBYTES        3
 197 #define CONFIG_SYS_NAND_OOBSIZE 16
 198 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 199
 200 #ifdef CONFIG_ENV_IS_IN_NAND
 201 /*
 202  * For NAND booting the environment is embedded in the U-Boot image. Please take
 203  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 204  */
 205 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 206 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 207 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 208 #endif
 209
 210 /*-----------------------------------------------------------------------
 211  * NAND FLASH
 212  *----------------------------------------------------------------------*/
 213 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 214 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 215 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 216
 217 /*-----------------------------------------------------------------------
 218  * DDR SDRAM
 219  *----------------------------------------------------------------------*/
 220 #define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
 221
 222 /*
 223  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 224  *
 225  * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
 226  *       SDRAM Controller DDR autocalibration values and takes a lot longer
 227  *       to run than Method_B.
 228  * (See the Method_A and Method_B algorithm discription in the file:
 229  *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
 230  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
 231  *
 232  * DDR Autocalibration Method_B is the default.
 233  */
 234 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 235 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
 236 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 237 #undef  CONFIG_PPC4xx_DDR_METHOD_A
 238 #endif
 239
 240 #define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 241
 242 /* DDR1/2 SDRAM Device Control Register Data Values */
 243 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
 244                                  SDRAM_RXBAS_SDSZ_256MB         | \
 245                                  SDRAM_RXBAS_SDAM_MODE7         | \
 246                                  SDRAM_RXBAS_SDBE_ENABLE)
 247 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
 248 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
 249 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
 250 #define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN          | \
 251                                  SDRAM_MCOPT1_8_BANKS           | \
 252                                  SDRAM_MCOPT1_DDR2_TYPE         | \
 253                                  SDRAM_MCOPT1_QDEP              | \
 254                                  SDRAM_MCOPT1_DCOO_DISABLED)
 255 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 256 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
 257                                  SDRAM_MODT_EB0R_ENABLE)
 258 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
 259 #define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
 260                                  SDRAM_CODT_CKLZ_36OHM          | \
 261                                  SDRAM_CODT_DQS_1_8_V_DDR2      | \
 262                                  SDRAM_CODT_IO_NMODE)
 263 #define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 264 #define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE                   | \
 265                 SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
 266                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 267 #define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE                   | \
 268                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 269                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 270                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 271                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 272 #define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE                   | \
 273                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 274                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 275                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
 276                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 277 #define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE                   | \
 278                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 279                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 280                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
 281                 SDRAM_INITPLR_IMA_ENCODE(0))
 282 #define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE                   | \
 283                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 284                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 285                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 286                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 287                                          JEDEC_MA_EMR_RTT_75OHM))
 288 #define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE                   | \
 289                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 290                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 291                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 292                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 293                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 294                                          JEDEC_MA_MR_BLEN_4 | \
 295                                          JEDEC_MA_MR_DLL_RESET))
 296 #define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE                   | \
 297                 SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 298                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 299                 SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
 300                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 301 #define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE                   | \
 302                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 303                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 304 #define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE                   | \
 305                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 306                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 307 #define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE                   | \
 308                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 309                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 310 #define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE                   | \
 311                 SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 312                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 313 #define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE                   | \
 314                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 315                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 316                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 317                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 318                                          JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 319                                          JEDEC_MA_MR_BLEN_4))
 320 #define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE                   | \
 321                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 322                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 323                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 324                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
 325                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 326                                          JEDEC_MA_EMR_DQS_DISABLE | \
 327                                          JEDEC_MA_EMR_RTT_DISABLED | \
 328                                          JEDEC_MA_EMR_ODS_NORMAL))
 329 #define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE                   | \
 330                 SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 331                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 332                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 333                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
 334                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 335                                          JEDEC_MA_EMR_DQS_DISABLE | \
 336                                          JEDEC_MA_EMR_RTT_DISABLED | \
 337                                          JEDEC_MA_EMR_ODS_NORMAL))
 338 #define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
 339 #define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
 340 #define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
 341                                  SDRAM_RQDC_RQFD_ENCODE(56))
 342 #define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
 343 #define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 344 #define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
 345                                  SDRAM_DLCR_DLCS_CONT_DONE      | \
 346                                  SDRAM_DLCR_DLCV_ENCODE(165))
 347 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
 348 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
 349 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
 350                                  SDRAM_SDTR1_RTW_2_CLK  | \
 351                                  SDRAM_SDTR1_RTRO_1_CLK)
 352 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK          | \
 353                                  SDRAM_SDTR2_WTR_2_CLK          | \
 354                                  SDRAM_SDTR2_XSNR_32_CLK        | \
 355                                  SDRAM_SDTR2_WPC_4_CLK          | \
 356                                  SDRAM_SDTR2_RPC_2_CLK          | \
 357                                  SDRAM_SDTR2_RP_3_CLK           | \
 358                                  SDRAM_SDTR2_RRD_2_CLK)
 359 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 360                                  SDRAM_SDTR3_RC_ENCODE(11)      | \
 361                                  SDRAM_SDTR3_XCS                | \
 362                                  SDRAM_SDTR3_RFC_ENCODE(26))
 363 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
 364                                  SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
 365                                  SDRAM_MMODE_BLEN_4)
 366 #define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
 367                                  SDRAM_MEMODE_RTT_75OHM)
 368
 369 /*-----------------------------------------------------------------------
 370  * I2C
 371  *----------------------------------------------------------------------*/
 372 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 373
 374 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
 375 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 376 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 377 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 378
 379 /* I2C bootstrap EEPROM */
 380 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 381 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 382 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 383
 384 /* Standard DTT sensor configuration */
 385 #define CONFIG_DTT_DS1775       1
 386 #define CONFIG_DTT_SENSORS      { 0 }
 387 #define CONFIG_SYS_I2C_DTT_ADDR 0x48
 388
 389 /* RTC configuration */
 390 #define CONFIG_RTC_DS1338       1
 391 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 392
 393 /*-----------------------------------------------------------------------
 394  * Ethernet
 395  *----------------------------------------------------------------------*/
 396 #define CONFIG_M88E1111_PHY     1
 397 #define CONFIG_IBM_EMAC4_V4     1
 398 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 399 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 400
 401 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 402 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 403
 404 #define CONFIG_HAS_ETH0         1
 405
 406 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 407 #define CONFIG_PHY1_ADDR        2
 408
 409 /* Debug messages for the DDR autocalibration */
 410 #define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
 411
 412 /*
 413  * Default environment variables
 414  */
 415 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 416         CONFIG_AMCC_DEF_ENV                                             \
 417         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 418         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 419         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 420         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 421         "logversion=2\0"                                                \
 422         "kernel_addr=fc000000\0"                                        \
 423         "fdt_addr=fc1e0000\0"                                           \
 424         "ramdisk_addr=fc200000\0"                                       \
 425         "pciconfighost=1\0"                                             \
 426         "pcie_mode=RP:RP\0"                                             \
 427         ""
 428
 429 /*
 430  * Commands additional to the ones defined in amcc-common.h
 431  */
 432 #define CONFIG_CMD_CHIP_CONFIG
 433 #define CONFIG_CMD_DATE
 434 #define CONFIG_CMD_NAND
 435 #define CONFIG_CMD_PCI
 436 #define CONFIG_CMD_SNTP
 437
 438 /*
 439  * Don't run the memory POST on the NAND-booting version. It will
 440  * overwrite part of the U-Boot image which is already loaded from NAND
 441  * to SDRAM.
 442  */
 443 #if defined(CONFIG_NAND_U_BOOT)
 444 #define CONFIG_SYS_POST_MEMORY_ON       0
 445 #else
 446 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 447 #endif
 448
 449 /* POST support */
 450 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 451                                  CONFIG_SYS_POST_CPU            | \
 452                                  CONFIG_SYS_POST_ETHER          | \
 453                                  CONFIG_SYS_POST_I2C            | \
 454                                  CONFIG_SYS_POST_MEMORY_ON      | \
 455                                  CONFIG_SYS_POST_UART)
 456
 457 /* Define here the base-addresses of the UARTs to test in POST */
 458 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 459                         CONFIG_SYS_NS16550_COM2 }
 460
 461 #define CONFIG_LOGBUFFER
 462 #define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
 463
 464 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 465
 466 /*-----------------------------------------------------------------------
 467  * PCI stuff
 468  *----------------------------------------------------------------------*/
 469 #define CONFIG_PCI                      /* include pci support          */
 470 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 471 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 472 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 473 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 474
 475 /*-----------------------------------------------------------------------
 476  * PCIe stuff
 477  *----------------------------------------------------------------------*/
 478 #define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
 479 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
 480
 481 #define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
 482 #define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
 483 #define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
 484
 485 #define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
 486 #define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
 487 #define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
 488
 489 #define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
 490 #define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
 491
 492 /* base address of inbound PCIe window */
 493 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
 494
 495 /*-----------------------------------------------------------------------
 496  * External Bus Controller (EBC) Setup
 497  *----------------------------------------------------------------------*/
 498 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 499 /* booting from NAND, so NAND chips select has to be on CS 0 */
 500 #define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
 501
 502 /* Memory Bank 1 (NOR-FLASH) initialization                                     */
 503 #define CONFIG_SYS_EBC_PB1AP            0x05806500
 504 #define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 505
 506 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 507 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 508 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 509 #else
 510 #define CONFIG_SYS_NAND_CS              1               /* NAND chip connected to CSx   */
 511
 512 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 513 #define CONFIG_SYS_EBC_PB0AP            0x05806500
 514 #define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 515
 516 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
 517 #define CONFIG_SYS_EBC_PB1AP            0x018003c0
 518 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 519 #endif
 520
 521 /* Memory Bank 2 (FPGA) initialization                                  */
 522 #define CONFIG_SYS_EBC_PB2AP            (EBC_BXAP_BME_ENABLED |         \
 523                                          EBC_BXAP_FWT_ENCODE(6) |       \
 524                                          EBC_BXAP_BWT_ENCODE(1) |       \
 525                                          EBC_BXAP_BCE_DISABLE |         \
 526                                          EBC_BXAP_BCT_2TRANS |          \
 527                                          EBC_BXAP_CSN_ENCODE(0) |       \
 528                                          EBC_BXAP_OEN_ENCODE(0) |       \
 529                                          EBC_BXAP_WBN_ENCODE(3) |       \
 530                                          EBC_BXAP_WBF_ENCODE(1) |       \
 531                                          EBC_BXAP_TH_ENCODE(4) |        \
 532                                          EBC_BXAP_RE_DISABLED |         \
 533                                          EBC_BXAP_SOR_DELAYED |         \
 534                                          EBC_BXAP_BEM_WRITEONLY |       \
 535                                          EBC_BXAP_PEN_DISABLED)
 536 #define CONFIG_SYS_EBC_PB2CR    (CONFIG_SYS_FPGA_BASE | 0x18000)
 537
 538 #define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
 539
 540 /*-----------------------------------------------------------------------
 541  * GPIO Setup
 542  *----------------------------------------------------------------------*/
 543 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 544 {                                                                                       \
 545 /* GPIO Core 0 */                                                                       \
 546 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 547 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 548 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 549 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 550 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 551 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 552 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 553 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 554 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 555 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 556 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 557 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 558 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 559 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 560 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 561 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 562 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 563 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 564 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 565 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 566 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 567 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 568 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 569 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 570 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 571 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 572 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 573 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 574 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
 575 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 576 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 577 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 578 }                                                                                               \
 579 }
 580
 581 /*-----------------------------------------------------------------------
 582  * Some Kilauea stuff..., mainly fpga registers
 583  */
 584 #define CONFIG_SYS_FPGA_REG_BASE                CONFIG_SYS_FPGA_BASE
 585 #define CONFIG_SYS_FPGA_FIFO_BASE               (CONFIG_SYS_FPGA_BASE | (1 << 10))
 586
 587 /* interrupt */
 588 #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT       0x80000000
 589 #define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT       0x40000000
 590 #define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT       0x20000000
 591 #define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT       0x10000000
 592 #define CONFIG_SYS_FPGA_PHY0_INT                0x08000000
 593 #define CONFIG_SYS_FPGA_PHY1_INT                0x04000000
 594 #define CONFIG_SYS_FPGA_SLIC0_INT               0x02000000
 595 #define CONFIG_SYS_FPGA_SLIC1_INT               0x01000000
 596
 597 /* DPRAM setting */
 598 /* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
 599 #define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE        0x00400000      /* 64 B */
 600 #define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE        0x00100000      /* 64 B */
 601 #define CONFIG_SYS_FPGA_DPRAM_RW_TYPE           0x00080000
 602 #define CONFIG_SYS_FPGA_DPRAM_RST               0x00040000
 603 #define CONFIG_SYS_FPGA_UART0_FO                0x00020000
 604 #define CONFIG_SYS_FPGA_UART1_FO                0x00010000
 605
 606 /* loopback */
 607 #define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK       0x00004000
 608 #define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK       0x00008000
 609 #define CONFIG_SYS_FPGA_SLIC0_ENABLE            0x00002000
 610 #define CONFIG_SYS_FPGA_SLIC1_ENABLE            0x00001000
 611 #define CONFIG_SYS_FPGA_SLIC0_CS                0x00000800
 612 #define CONFIG_SYS_FPGA_SLIC1_CS                0x00000400
 613 #define CONFIG_SYS_FPGA_USER_LED0               0x00000200
 614 #define CONFIG_SYS_FPGA_USER_LED1               0x00000100
 615
 616 #define CONFIG_SYS_FPGA_MAGIC_MASK              0xffff0000
 617 #define CONFIG_SYS_FPGA_MAGIC                   0xabcd0000
 618 #define CONFIG_SYS_FPGA_VER_MASK                0x0000ff00
 619
 620 #endif  /* __CONFIG_H */