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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/km/kmp204x-common.h
2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _CONFIG_KMP204X_H
9 #define _CONFIG_KMP204X_H
11 #define CONFIG_SYS_TEXT_BASE 0xfff40000
13 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
15 /* an additionnal option is required for UBI as subpage access is
16 * supported in u-boot */
17 #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
19 #define CONFIG_NAND_ECC_BCH
21 /* common KM defines */
22 #include "keymile-common.h"
24 #define CONFIG_SYS_RAMBOOT
25 #define CONFIG_RAMBOOT_PBL
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
29 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
31 /* High Level Configuration Options */
33 #define CONFIG_E500 /* BOOKE e500 family */
34 #define CONFIG_E500MC /* BOOKE e500mc family */
35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
36 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
37 #define CONFIG_MP /* support multiple processors */
39 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
40 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
41 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
42 #define CONFIG_PCIE1 /* PCIE controller 1 */
43 #define CONFIG_PCIE3 /* PCIE controller 3 */
44 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
45 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
47 #define CONFIG_SYS_DPAA_RMAN /* RMan */
49 #define CONFIG_FSL_LAW /* Use common FSL init code */
51 /* Environment in SPI Flash */
52 #define CONFIG_SYS_EXTRA_ENV_RELOC
53 #define CONFIG_ENV_IS_IN_SPI_FLASH
54 #define CONFIG_ENV_SPI_BUS 0
55 #define CONFIG_ENV_SPI_CS 0
56 #define CONFIG_ENV_SPI_MAX_HZ 20000000
57 #define CONFIG_ENV_SPI_MODE 0
58 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
59 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */
60 #define CONFIG_ENV_SECT_SIZE 0x010000
61 #define CONFIG_ENV_OFFSET_REDUND 0x110000
62 #define CONFIG_ENV_TOTAL_SIZE 0x020000
64 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
67 unsigned long get_board_sys_clk(unsigned long dummy
);
69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
72 * These can be toggled for performance analysis, otherwise use default.
74 #define CONFIG_SYS_CACHE_STASHING
75 #define CONFIG_BACKSIDE_L2_CACHE
76 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
77 #define CONFIG_BTB /* toggle branch predition */
79 #define CONFIG_ENABLE_36BIT_PHYS
81 #define CONFIG_ADDR_MAP
82 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
84 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
87 * Config the L3 Cache as L3 SRAM
89 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
90 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
91 CONFIG_RAMBOOT_TEXT_BASE)
92 #define CONFIG_SYS_L3_SIZE (1024 << 10)
93 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
95 #define CONFIG_SYS_DCSRBAR 0xf0000000
96 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
101 #define CONFIG_VERY_BIG_RAM
102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
105 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
106 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
108 #define CONFIG_DDR_SPD
109 #define CONFIG_SYS_FSL_DDR3
110 #define CONFIG_FSL_DDR_INTERACTIVE
112 #define CONFIG_SYS_SPD_BUS_NUM 0
113 #define SPD_EEPROM_ADDRESS 0x54
114 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
116 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
119 /******************************************************************************
121 * ... -------------------------------------------------------
122 * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
123 * ... |<------------------- pram -------------------------->|
124 * ... -------------------------------------------------------
126 * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
127 * @CONFIG_KM_PHRAM: address for /var
128 * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
129 * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
132 /* size of rootfs in RAM */
133 #define CONFIG_KM_ROOTFSSIZE 0x0
134 /* pseudo-non volatile RAM [hex] */
135 #define CONFIG_KM_PNVRAM 0x80000
136 /* physical RAM MTD size [hex] */
137 #define CONFIG_KM_PHRAM 0x100000
138 /* reserved pram area at the end of memory [hex]
139 * u-boot reserves some memory for the MP boot page */
140 #define CONFIG_KM_RESERVED_PRAM 0x1000
141 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
142 * is not valid yet, which is the case for when u-boot copies itself to RAM */
143 #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
145 #define CONFIG_KM_CRAMFS_ADDR 0x2000000
146 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
147 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
150 * Local Bus Definitions
153 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
154 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2)
157 #define CONFIG_NAND_FSL_ELBC
158 #define CONFIG_SYS_NAND_BASE 0xffa00000
159 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
161 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
162 #define CONFIG_SYS_MAX_NAND_DEVICE 1
163 #define CONFIG_CMD_NAND
164 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
168 /* NAND flash config */
169 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
170 | BR_PS_8 /* Port Size = 8 bit */ \
171 | BR_MS_FCM /* MSEL = FCM */ \
174 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
175 | OR_FCM_BCTLD /* LBCTL not ass */ \
176 | OR_FCM_SCY_1 /* 1 clk wait cycle */ \
177 | OR_FCM_RST /* 1 clk read setup */ \
178 | OR_FCM_PGS /* Large page size */ \
179 | OR_FCM_CST) /* 0.25 command setup */
181 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
182 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
185 #define CONFIG_SYS_QRIO_BASE 0xfb000000
186 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
188 #define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
189 | BR_PS_8 /* Port Size 8 bits */ \
190 | BR_DECC_OFF /* no error corr */ \
191 | BR_MS_GPCM /* MSEL = GPCM */ \
194 #define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \
195 | OR_GPCM_BCTLD /* no LCTL assert */ \
196 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
197 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
198 | OR_GPCM_TRLX /* relaxed tmgs */ \
199 | OR_GPCM_EAD) /* extra bus clk cycles */
201 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
202 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
204 /* bootcounter in QRIO */
205 #define CONFIG_BOOTCOUNT_LIMIT
206 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
208 #define CONFIG_BOARD_EARLY_INIT_F
209 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
210 #define CONFIG_MISC_INIT_F
211 #define CONFIG_MISC_INIT_R
212 #define CONFIG_LAST_STAGE_INIT
214 #define CONFIG_HWCONFIG
216 /* define to use L1 as initial stack */
217 #define CONFIG_L1_INIT_RAM
218 #define CONFIG_SYS_INIT_RAM_LOCK
219 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
220 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
221 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
222 /* The assembler doesn't like typecast */
223 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
224 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
225 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
226 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
228 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
229 GENERATED_GBL_DATA_SIZE)
230 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
233 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
234 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
236 /* Serial Port - controlled on board with jumper J8
240 #define CONFIG_CONS_INDEX 1
241 #define CONFIG_SYS_NS16550_SERIAL
242 #define CONFIG_SYS_NS16550_REG_SIZE 1
243 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
245 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
246 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
247 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
248 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
250 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
254 #define CONFIG_SYS_I2C
255 #define CONFIG_SYS_I2C_INIT_BOARD
256 #define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
257 #define CONFIG_SYS_NUM_I2C_BUSES 3
258 #define CONFIG_SYS_I2C_MAX_HOPS 1
259 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
260 #define CONFIG_I2C_MULTI_BUS
261 #define CONFIG_I2C_CMD_TREE
262 #define CONFIG_SYS_FSL_I2C_SPEED 400000
263 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
264 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
265 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
266 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
267 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
270 void set_sda(int state
);
271 void set_scl(int state
);
276 #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
279 * eSPI - Enhanced SPI
281 #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
282 #define CONFIG_SF_DEFAULT_SPEED 20000000
283 #define CONFIG_SF_DEFAULT_MODE 0
287 * Memory space is mapped 1-1, but I/O space must start from 0.
290 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
291 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
292 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
293 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
294 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
295 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
296 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
297 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
298 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
300 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
301 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
302 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
303 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
304 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
305 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
306 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
307 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
308 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
311 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
312 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
313 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
314 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
315 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
316 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
317 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
318 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
319 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
320 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
321 CONFIG_SYS_BMAN_CENA_SIZE)
322 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
323 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
324 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
325 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
326 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
327 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
328 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
329 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
330 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
331 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
332 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
333 CONFIG_SYS_QMAN_CENA_SIZE)
334 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
335 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
337 #define CONFIG_SYS_DPAA_FMAN
338 #define CONFIG_SYS_DPAA_PME
339 /* Default address of microcode for the Linux Fman driver
340 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
341 * ucode is stored after env, so we got 0x120000.
343 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
344 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
345 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
346 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
348 #define CONFIG_FMAN_ENET
349 #define CONFIG_PHYLIB_10G
350 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
352 #define CONFIG_PCI_INDIRECT_BRIDGE
354 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
355 #define CONFIG_DOS_PARTITION
357 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
358 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
359 #define CONFIG_SYS_TBIPA_VALUE 8
360 #define CONFIG_PHYLIB /* recommended PHY management */
361 #define CONFIG_ETHPRIME "FM1@DTSEC5"
362 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
367 #define CONFIG_LOADS_ECHO /* echo on for serial download */
368 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
373 #define CONFIG_WATCHDOG /* enable CPU watchdog */
374 #define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */
375 #define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
379 * additionnal command line configuration.
381 #define CONFIG_CMD_PCI
382 #define CONFIG_CMD_ERRATA
384 /* we don't need flash support */
385 #define CONFIG_SYS_NO_FLASH
386 #undef CONFIG_FLASH_CFI_MTD
387 #undef CONFIG_JFFS2_CMDLINE
390 * For booting Linux, the board info and command line data
391 * have to be in the first 64 MB of memory, since this is
392 * the maximum mapped by the Linux kernel during initialization.
394 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
395 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
397 #ifdef CONFIG_CMD_KGDB
398 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
401 #define __USB_PHY_TYPE utmi
402 #define CONFIG_USB_EHCI_FSL
405 * Environment Configuration
407 #define CONFIG_ENV_OVERWRITE
408 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
409 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
412 #ifndef MTDIDS_DEFAULT
413 # define MTDIDS_DEFAULT "nand0=fsl_elbc_nand"
414 #endif /* MTDIDS_DEFAULT */
416 #ifndef MTDPARTS_DEFAULT
417 # define MTDPARTS_DEFAULT "mtdparts=" \
419 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
420 #endif /* MTDPARTS_DEFAULT */
422 /* architecture specific default bootargs */
423 #define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
425 /* FIXME: FDT_ADDR is unspecified */
426 #define CONFIG_KM_DEF_ENV_CPU \
427 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
429 "cramfsload ${fdt_addr_r} " \
430 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
431 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
432 "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
434 "sf probe 0;sf erase 0 +${filesize};" \
435 "sf write ${load_addr_r} 0 ${filesize};\0" \
436 "set_fdthigh=true\0" \
440 #define CONFIG_HW_ENV_SETTINGS \
441 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
442 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
445 #define CONFIG_KM_NEW_ENV \
446 "newenv=sf probe 0;" \
447 "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
448 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
450 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
451 #ifndef CONFIG_KM_DEF_ARCH
452 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
455 #define CONFIG_EXTRA_ENV_SETTINGS \
459 CONFIG_HW_ENV_SETTINGS \
460 "EEprom_ivm=pca9547:70:9\0" \
463 #endif /* _CONFIG_KMP204X_H */