include/configs/legoev3.h

   1 /*
   2  * Copyright (C) 2016 David Lechner <david@lechnology.com>
   3  *
   4  * Based on da850evm.h
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * Based on davinci_dvevm.h. Original Copyrights follow:
   9  *
  10  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * SoC Configuration
  20  */
  21 #define CONFIG_MACH_DAVINCI_DA850_EVM
  22 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
  23 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
  24 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  25 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  26 #define CONFIG_SYS_OSCIN_FREQ           24000000
  27 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  28 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  29 #define CONFIG_SYS_DA850_DDR_INIT
  30
  31 #define CONFIG_SYS_TEXT_BASE            0xc1080000
  32
  33 /*
  34  * Memory Info
  35  */
  36 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  37 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  38 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  39 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  40
  41 /* memtest start addr */
  42 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  43
  44 /* memtest will be run on 16MB */
  45 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  46
  47 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  48
  49 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  50         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  51         DAVINCI_SYSCFG_SUSPSRC_SPI0 |           \
  52         DAVINCI_SYSCFG_SUSPSRC_UART1 |          \
  53         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  54         DAVINCI_SYSCFG_SUSPSRC_I2C)
  55
  56 /*
  57  * PLL configuration
  58  */
  59 #define CONFIG_SYS_DV_CLKMODE          0
  60 #define CONFIG_SYS_DA850_PLL0_POSTDIV  1
  61 #define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
  62 #define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
  63 #define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
  64 #define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
  65 #define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
  66 #define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
  67 #define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
  68
  69 #define CONFIG_SYS_DA850_PLL1_POSTDIV  1
  70 #define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
  71 #define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
  72 #define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
  73
  74 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  75 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  76
  77 /*
  78  * DDR2 memory configuration
  79  */
  80 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  81                                         DV_DDR_PHY_EXT_STRBEN | \
  82                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  83
  84 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  85         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  86         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  87         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  88         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  89         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  90         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  91         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  92
  93 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  94 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  95
  96 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  97         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  98         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  99         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
 100         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
 101         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
 102         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
 103         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
 104         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
 105
 106 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
 107         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
 108         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
 109         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
 110         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
 111         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 112         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 113         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 114
 115 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 116 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 117
 118 /*
 119  * Serial Driver info
 120  */
 121 #define CONFIG_SYS_NS16550_SERIAL
 122 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 123 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */
 124 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 125 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
 126 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
 127
 128 #define CONFIG_SPI
 129 #define CONFIG_DAVINCI_SPI
 130 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI0_BASE
 131 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI0_CLKID)
 132 #define CONFIG_SF_DEFAULT_SPEED         50000000
 133 #define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
 134
 135 /*
 136  * I2C Configuration
 137  */
 138 #define CONFIG_SYS_I2C
 139 #define CONFIG_SYS_I2C_DAVINCI
 140 #define CONFIG_SYS_DAVINCI_I2C_SPEED            400000
 141 #define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
 142
 143 /*
 144  * U-Boot general configuration
 145  */
 146 #define CONFIG_BOARD_EARLY_INIT_F
 147 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 148 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 149 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 150 #define CONFIG_SYS_MAXARGS      16 /* max number of command args */
 151 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 152 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 153 #define CONFIG_AUTO_COMPLETE
 154 #define CONFIG_CMDLINE_EDITING
 155 #define CONFIG_SYS_LONGHELP
 156 #define CONFIG_CRC32_VERIFY
 157 #define CONFIG_MX_CYCLIC
 158
 159 /*
 160  * Linux Information
 161  */
 162 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 163 #define CONFIG_HWCONFIG         /* enable hwconfig */
 164 #define CONFIG_CMDLINE_TAG
 165 #define CONFIG_REVISION_TAG
 166 #define CONFIG_SERIAL_TAG
 167 #define CONFIG_SETUP_MEMORY_TAGS
 168 #define CONFIG_SETUP_INITRD_TAG
 169 #define CONFIG_BOOTCOMMAND \
 170         "if mmc rescan; then " \
 171                 "if run loadbootscr; then " \
 172                         "run bootscript; " \
 173                 "else " \
 174                         "if run loadimage; then " \
 175                                 "run mmcargs; " \
 176                                 "run mmcboot; " \
 177                         "else " \
 178                                 "run flashargs; " \
 179                                 "run flashboot; " \
 180                         "fi; " \
 181                 "fi; " \
 182         "else " \
 183                 "run flashargs; " \
 184                 "run flashboot; " \
 185         "fi"
 186 #define CONFIG_EXTRA_ENV_SETTINGS \
 187         "hostname=EV3\0" \
 188         "memsize=64M\0" \
 189         "filesyssize=10M\0" \
 190         "verify=n\0" \
 191         "console=ttyS1,115200n8\0" \
 192         "bootscraddr=0xC0600000\0" \
 193         "loadaddr=0xC0007FC0\0" \
 194         "filesysaddr=0xC1180000\0" \
 195         "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \
 196         "mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \
 197         "mmcboot=bootm ${loadaddr}\0" \
 198         "flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \
 199         "flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \
 200         "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \
 201         "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \
 202         "bootscript=source ${bootscraddr}\0" \
 203
 204 /*
 205  * U-Boot commands
 206  */
 207 #define CONFIG_CMD_DIAG
 208 #define CONFIG_CMD_SAVES
 209
 210 #ifdef CONFIG_CMD_BDI
 211 #define CONFIG_CLOCKS
 212 #endif
 213
 214 #define CONFIG_ENV_IS_NOWHERE
 215 #define CONFIG_SYS_NO_FLASH
 216 #define CONFIG_ENV_SIZE         (16 << 10)
 217
 218 /* SD/MMC configuration */
 219 #define CONFIG_MMC
 220 #define CONFIG_DAVINCI_MMC_SD1
 221 #define CONFIG_GENERIC_MMC
 222 #define CONFIG_DAVINCI_MMC
 223
 224 /*
 225  * Enable MMC commands only when
 226  * MMC support is present
 227  */
 228 #ifdef CONFIG_MMC
 229 #define CONFIG_DOS_PARTITION
 230 #endif
 231
 232 /* additions for new relocation code, must added to all boards */
 233 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 234
 235 #define CONFIG_SYS_INIT_SP_ADDR         0x80010000
 236
 237 #endif /* __CONFIG_H */