include/configs/logodl.h

   1 /*
   2  * (C) Copyright 2003
   3  * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
   4  *
   5  * Configuration for the Logotronic DL board.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * include/configs/logodl.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * If we are developing, we might want to start U-Boot from ram
  35  * so we MUST NOT initialize critical regs like mem-timing ...
  36  */
  37 #define CONFIG_INIT_CRITICAL            /* undef for developing */
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43 #define CONFIG_PXA250           1       /* This is an PXA250 CPU            */
  44 #define CONFIG_GEALOG           1       /* on a Logotronic GEALOG SG board  */
  45
  46 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff      */
  47                                         /* for timer/console/ethernet       */
  48 /*
  49  * Hardware drivers
  50  */
  51
  52 /*
  53  * select serial console configuration
  54  */
  55 #define CONFIG_FFUART           1       /* we use FFUART                    */
  56
  57 /* allow to overwrite serial and ethaddr */
  58 #define CONFIG_ENV_OVERWRITE
  59
  60 #define CONFIG_BAUDRATE         19200
  61 /*#define CONFIG_MISC_INIT_R    1       / * we have a misc_init_r() function */
  62 #undef CONFIG_MISC_INIT_R               /* FIXME                            */
  63
  64 #define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO)
  65 /* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
  66 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any)   */
  67 #include <cmd_confdefs.h>
  68
  69 #define CONFIG_BOOTDELAY        3
  70 /* #define CONFIG_BOOTARGS      "root=/dev/nfs ip=bootp console=ttyS0,19200" */
  71 #define CONFIG_BOOTARGS         "console=ttyS0,19200"
  72 #define CONFIG_ETHADDR          FF:FF:FF:FF:FF:FF
  73 #define CONFIG_NETMASK          255.255.255.0
  74 #define CONFIG_IPADDR           192.168.1.56
  75 #define CONFIG_SERVERIP         192.168.1.2
  76 #define CONFIG_BOOTCOMMAND      "bootm 0x40000"
  77 #define CONFIG_SHOW_BOOT_PROGRESS
  78
  79 #define CONFIG_CMDLINE_TAG      1
  80
  81 /*
  82  * Miscellaneous configurable options
  83  */
  84
  85 /*
  86  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
  87  * used for the RAM copy of the uboot code
  88  *
  89  */
  90 #define CFG_MALLOC_LEN          (256*1024)
  91
  92 #define CFG_LONGHELP                            /* undef to save memory         */
  93 #define CFG_PROMPT              "uboot> "       /* Monitor Command Prompt       */
  94 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  95 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  96 #define CFG_MAXARGS             16              /* max number of command args   */
  97 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  98
  99 #define CFG_MEMTEST_START       0x08000000      /* memtest works on             */
 100 #define CFG_MEMTEST_END         0x0800ffff      /* 64 KiB                       */
 101
 102 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 103
 104 #define CFG_LOAD_ADDR           0x08000000      /* load kernel to this address   */
 105
 106 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 107                                                 /* RS: the oscillator is actually 3680130?? */
 108
 109 #define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 110                                                 /* 0101000001 */
 111                                                 /*      ^^^^^ Memory Speed 99.53 MHz         */
 112                                                 /*    ^^      Run Mode Speed = 2x Mem Speed  */
 113                                                 /* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
 114
 115 #define CFG_MONITOR_LEN         0x20000         /* 128 KiB */
 116
 117                                                 /* valid baudrates */
 118 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 119
 120 /*
 121  * SMSC91C111 Network Card
 122  */
 123 /*#define CONFIG_DRIVER_SMC91111                1       */
 124 /*#define CONFIG_SMC91111_BASE          0x10000000 / * chip select 4         */
 125 /*#undef  CONFIG_SMC_USE_32_BIT                    / * 16 bit bus access     */
 126 /*#undef  CONFIG_SMC_91111_EXT_PHY                 / * we use internal phy   */
 127 /*#undef  CONFIG_SHOW_ACTIVITY  */
 128 /*#define CONFIG_NET_RETRY_COUNT                10         / * # of retries          */
 129
 130 /*
 131  * Stack sizes
 132  *
 133  * The stack sizes are set up in start.S using the settings below
 134  */
 135 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 136 #ifdef  CONFIG_USE_IRQ
 137 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 138 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 139 #endif
 140
 141 /*
 142  * Physical Memory Map
 143  */
 144 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of RAM    */
 145 #define PHYS_SDRAM_1            0x08000000      /* SRAM Bank #1             */
 146 #define PHYS_SDRAM_1_SIZE       (4*1024*1024)   /* 4 MB                     */
 147
 148 #define PHYS_FLASH_1            0x00000000      /* Flash Bank #1            */
 149 #define PHYS_FLASH_2            0x01000000      /* Flash Bank #2            */
 150 #define PHYS_FLASH_SIZE         (32*1024*1024)  /* 32 MB                    */
 151
 152 #define CFG_DRAM_BASE           PHYS_SDRAM_1    /* RAM starts here          */
 153 #define CFG_DRAM_SIZE           PHYS_SDRAM_1_SIZE
 154
 155 #define CFG_FLASH_BASE          PHYS_FLASH_1
 156
 157
 158 /*
 159  * GPIO settings
 160  *
 161  * GP?? == FOOBAR    is 0/1
 162  */
 163
 164 #define _BIT0       0x00000001
 165 #define _BIT1       0x00000002
 166 #define _BIT2       0x00000004
 167 #define _BIT3       0x00000008
 168
 169 #define _BIT4       0x00000010
 170 #define _BIT5       0x00000020
 171 #define _BIT6       0x00000040
 172 #define _BIT7       0x00000080
 173
 174 #define _BIT8       0x00000100
 175 #define _BIT9       0x00000200
 176 #define _BIT10      0x00000400
 177 #define _BIT11      0x00000800
 178
 179 #define _BIT12      0x00001000
 180 #define _BIT13      0x00002000
 181 #define _BIT14      0x00004000
 182 #define _BIT15      0x00008000
 183
 184 #define _BIT16      0x00010000
 185 #define _BIT17      0x00020000
 186 #define _BIT18      0x00040000
 187 #define _BIT19      0x00080000
 188
 189 #define _BIT20      0x00100000
 190 #define _BIT21      0x00200000
 191 #define _BIT22      0x00400000
 192 #define _BIT23      0x00800000
 193
 194 #define _BIT24      0x01000000
 195 #define _BIT25      0x02000000
 196 #define _BIT26      0x04000000
 197 #define _BIT27      0x08000000
 198
 199 #define _BIT28      0x10000000
 200 #define _BIT29      0x20000000
 201 #define _BIT30      0x40000000
 202 #define _BIT31      0x80000000
 203
 204
 205 #define CFG_LED_A_BIT           (_BIT18)
 206 #define CFG_LED_A_SR            GPSR0
 207 #define CFG_LED_A_CR            GPCR0
 208
 209 #define CFG_LED_B_BIT           (_BIT16)
 210 #define CFG_LED_B_SR            GPSR1
 211 #define CFG_LED_B_CR            GPCR1
 212
 213
 214 /* LED A: off, LED B: off */
 215 #define CFG_GPSR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
 216 #define CFG_GPSR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
 217 #define CFG_GPSR2_VAL       (_BIT14+_BIT15+_BIT16)
 218
 219 #define CFG_GPCR0_VAL       0x00000000
 220 #define CFG_GPCR1_VAL       0x00000000
 221 #define CFG_GPCR2_VAL       0x00000000
 222
 223 #define CFG_GPDR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
 224 #define CFG_GPDR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
 225 #define CFG_GPDR2_VAL       (_BIT14+_BIT15+_BIT16)
 226
 227 #define CFG_GAFR0_L_VAL     (_BIT22+_BIT24+_BIT31)
 228 #define CFG_GAFR0_U_VAL     (_BIT15+_BIT17+_BIT19+\
 229                              _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
 230 #define CFG_GAFR1_L_VAL     (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
 231                              _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
 232 #define CFG_GAFR1_U_VAL     (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
 233 #define CFG_GAFR2_L_VAL     (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
 234                              _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
 235 #define CFG_GAFR2_U_VAL     (_BIT1)
 236
 237 #define CFG_PSSR_VAL        (0x20)
 238
 239 /*
 240  * Memory settings
 241  */
 242 #define CFG_MSC0_VAL    0x123c2980
 243 #define CFG_MSC1_VAL    0x123c2661
 244 #define CFG_MSC2_VAL    0x7ff87ff8
 245
 246
 247 /* no sdram/pcmcia here */
 248 #define CFG_MDCNFG_VAL          0x00000000
 249 #define CFG_MDREFR_VAL          0x00000000
 250 #define CFG_MDREFR_VAL_100      0x00000000
 251 #define CFG_MDMRS_VAL           0x00000000
 252
 253 /* only SRAM */
 254 #define SXCNFG_SETTINGS 0x00000000
 255
 256 /*
 257  * PCMCIA and CF Interfaces
 258  */
 259
 260 #define CFG_MECR_VAL        0x00000000
 261 #define CFG_MCMEM0_VAL      0x00010504
 262 #define CFG_MCMEM1_VAL      0x00010504
 263 #define CFG_MCATT0_VAL      0x00010504
 264 #define CFG_MCATT1_VAL      0x00010504
 265 #define CFG_MCIO0_VAL       0x00004715
 266 #define CFG_MCIO1_VAL       0x00004715
 267
 268
 269 /*
 270  * FLASH and environment organization
 271  */
 272 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 273 #define CFG_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
 274
 275 /* timeout values are in ticks */
 276 #define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
 277 #define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
 278
 279 /* FIXME */
 280 #define CFG_ENV_IS_IN_FLASH     1
 281 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)        /* Addr of Environment Sector   */
 282 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 283
 284 #endif  /* __CONFIG_H */
 285