include/configs/ls1021aiot.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  13
  14 #define CONFIG_SYS_FSL_CLK
  15
  16 /*
  17  * Size of malloc() pool
  18  */
  19 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  20
  21 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  22 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  23
  24 /* XHCI Support - enabled by default */
  25 #define CONFIG_HAS_FSL_XHCI_USB
  26
  27 #ifdef CONFIG_HAS_FSL_XHCI_USB
  28 #define CONFIG_USB_XHCI_FSL
  29 #define CONFIG_USB_XHCI_DWC3
  30 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
  31 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
  32 #endif
  33
  34 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
  35 #define CONFIG_USB_STORAGE
  36 #define CONFIG_CMD_EXT2
  37 #endif
  38
  39 /*
  40  * Generic Timer Definitions
  41  */
  42 #define GENERIC_TIMER_CLK               12500000
  43
  44 #define CONFIG_SYS_CLK_FREQ             100000000
  45 #define CONFIG_DDR_CLK_FREQ             100000000
  46
  47 /*
  48  * DDR: 800 MHz ( 1600 MT/s data rate )
  49  */
  50
  51 #define DDR_SDRAM_CFG                   0x470c0008
  52 #define DDR_CS0_BNDS                    0x008000bf
  53 #define DDR_CS0_CONFIG                  0x80014302
  54 #define DDR_TIMING_CFG_0                0x50550004
  55 #define DDR_TIMING_CFG_1                0xbcb38c56
  56 #define DDR_TIMING_CFG_2                0x0040d120
  57 #define DDR_TIMING_CFG_3                0x010e1000
  58 #define DDR_TIMING_CFG_4                0x00000001
  59 #define DDR_TIMING_CFG_5                0x03401400
  60 #define DDR_SDRAM_CFG_2                 0x00401010
  61 #define DDR_SDRAM_MODE                  0x00061c60
  62 #define DDR_SDRAM_MODE_2                0x00180000
  63 #define DDR_SDRAM_INTERVAL              0x18600618
  64 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  65 #define DDR_DDR_WRLVL_CNTL_2    0x05060607
  66 #define DDR_DDR_WRLVL_CNTL_3    0x05050505
  67 #define DDR_DDR_CDR1                    0x80040000
  68 #define DDR_DDR_CDR2                    0x00000001
  69 #define DDR_SDRAM_CLK_CNTL              0x02000000
  70 #define DDR_DDR_ZQ_CNTL                 0x89080600
  71 #define DDR_CS0_CONFIG_2                0
  72 #define DDR_SDRAM_CFG_MEM_EN    0x80000000
  73 #define SDRAM_CFG2_D_INIT               0x00000010
  74 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
  75 #define SDRAM_CFG2_FRC_SR               0x80000000
  76 #define SDRAM_CFG_BI                    0x00000001
  77
  78 #ifdef CONFIG_RAMBOOT_PBL
  79 #define CONFIG_SYS_FSL_PBL_PBI  \
  80         board/freescale/ls1021aiot/ls102xa_pbi.cfg
  81 #endif
  82
  83 #ifdef CONFIG_SD_BOOT
  84 #define CONFIG_SYS_FSL_PBL_RCW  \
  85         board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
  86 #define CONFIG_SPL_FRAMEWORK
  87 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  88 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  89 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  90 #define CONFIG_SPL_ENV_SUPPORT
  91 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  92 #define CONFIG_SPL_I2C_SUPPORT
  93 #define CONFIG_SPL_WATCHDOG_SUPPORT
  94 #define CONFIG_SPL_SERIAL_SUPPORT
  95 #define CONFIG_SPL_MMC_SUPPORT
  96 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
  97
  98 #define CONFIG_SPL_TEXT_BASE    0x10000000
  99 #define CONFIG_SPL_MAX_SIZE             0x1a000
 100 #define CONFIG_SPL_STACK                0x1001d000
 101 #define CONFIG_SPL_PAD_TO               0x1c000
 102 #define CONFIG_SYS_TEXT_BASE    0x82000000
 103
 104 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
 105                 CONFIG_SYS_MONITOR_LEN)
 106 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 107 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 108 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 109 #define CONFIG_SYS_MONITOR_LEN          0x80000
 110 #endif
 111
 112 #ifdef CONFIG_QSPI_BOOT
 113 #define CONFIG_SYS_TEXT_BASE            0x40010000
 114 #endif
 115
 116 #define CONFIG_NR_DRAM_BANKS            1
 117
 118 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
 119 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 120
 121 /*
 122  * Serial Port
 123  */
 124 #define CONFIG_CONS_INDEX               1
 125 #define CONFIG_SYS_NS16550_SERIAL
 126 #define CONFIG_SYS_NS16550_REG_SIZE     1
 127 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 128
 129 /*
 130  * I2C
 131  */
 132 #define CONFIG_CMD_I2C
 133 #define CONFIG_SYS_I2C
 134 #define CONFIG_SYS_I2C_MXC
 135 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 136 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 137 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 138
 139 /* EEPROM */
 140 #define CONFIG_ID_EEPROM
 141 #define CONFIG_SYS_I2C_EEPROM_NXID
 142 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 143 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x51
 144 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 145
 146 /*
 147  * MMC
 148  */
 149 #define CONFIG_CMD_MMC
 150 #define CONFIG_FSL_ESDHC
 151
 152 /* SATA */
 153 #define CONFIG_CMD_SCSI
 154 #define CONFIG_LIBATA
 155 #define CONFIG_SCSI_AHCI
 156 #define CONFIG_SCSI_AHCI_PLAT
 157 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI
 158 #define PCI_DEVICE_ID_FREESCALE_AHCI    0x0440
 159 #endif
 160 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_FREESCALE, \
 161         PCI_DEVICE_ID_FREESCALE_AHCI}
 162
 163 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
 164 #define CONFIG_SYS_SCSI_MAX_LUN         1
 165 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 166                 CONFIG_SYS_SCSI_MAX_LUN)
 167
 168 #define CONFIG_CMD_FAT
 169
 170 /* SPI */
 171 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 172 #define CONFIG_SPI_FLASH_SPANSION
 173
 174 /* QSPI */
 175 #define QSPI0_AMBA_BASE                 0x40000000
 176 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 177 #define FSL_QSPI_FLASH_NUM              2
 178 #define CONFIG_SPI_FLASH_BAR
 179 #define CONFIG_SPI_FLASH_SPANSION
 180 #endif
 181
 182 /* DM SPI */
 183 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 184 #define CONFIG_CMD_SF
 185 #define CONFIG_DM_SPI_FLASH
 186 #endif
 187
 188 /*
 189  * eTSEC
 190  */
 191 #define CONFIG_TSEC_ENET
 192
 193 #ifdef CONFIG_TSEC_ENET
 194 #define CONFIG_MII
 195 #define CONFIG_MII_DEFAULT_TSEC         1
 196 #define CONFIG_TSEC1                    1
 197 #define CONFIG_TSEC1_NAME               "eTSEC1"
 198 #define CONFIG_TSEC2                    1
 199 #define CONFIG_TSEC2_NAME               "eTSEC2"
 200
 201 #define TSEC1_PHY_ADDR                  1
 202 #define TSEC2_PHY_ADDR                  3
 203
 204 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 205 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 206
 207 #define TSEC1_PHYIDX                    0
 208 #define TSEC2_PHYIDX                    0
 209
 210 #define CONFIG_ETHPRIME                 "eTSEC2"
 211
 212 #define CONFIG_PHY_GIGE
 213 #define CONFIG_PHYLIB
 214 #define CONFIG_PHY_ATHEROS
 215
 216 #define CONFIG_HAS_ETH0
 217 #define CONFIG_HAS_ETH1
 218 #define CONFIG_HAS_ETH2
 219 #endif
 220
 221 /* PCIe */
 222 #define CONFIG_PCIE1            /* PCIE controler 1 */
 223 #define CONFIG_PCIE2            /* PCIE controler 2 */
 224
 225 #define FSL_PCIE_COMPAT         "fsl,ls1021a-pcie"
 226
 227 #ifdef CONFIG_PCI
 228 #define CONFIG_PCI_SCAN_SHOW
 229 #define CONFIG_CMD_PCI
 230 #endif
 231
 232 #define CONFIG_CMD_PING
 233 #define CONFIG_CMD_DHCP
 234 #define CONFIG_CMD_MII
 235
 236 #define CONFIG_CMDLINE_TAG
 237 #define CONFIG_CMDLINE_EDITING
 238
 239 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT)
 240 #undef  CONFIG_CMD_IMLS
 241 #endif
 242
 243 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 244 #define CONFIG_LAYERSCAPE_NS_ACCESS
 245 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 246 #define CONFIG_TIMER_CLK_FREQ           12500000
 247
 248 #define CONFIG_HWCONFIG
 249 #define HWCONFIG_BUFFER_SIZE            256
 250
 251 #define CONFIG_FSL_DEVICE_DISABLE
 252
 253 #define CONFIG_EXTRA_ENV_SETTINGS       \
 254         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 255 "initrd_high=0xffffffff\0"      \
 256 "fdt_high=0xffffffff\0"
 257
 258 /*
 259  * Miscellaneous configurable options
 260  */
 261 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 262 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 263 #define CONFIG_AUTO_COMPLETE
 264 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 265 #define CONFIG_SYS_PBSIZE               \
 266         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 267 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 268 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 269
 270 #define CONFIG_CMD_GREPENV
 271 #define CONFIG_CMD_MEMINFO
 272
 273 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 274
 275 #define CONFIG_LS102XA_STREAM_ID
 276
 277 /*
 278  * Stack sizes
 279  * The stack sizes are set up in start.S using the settings below
 280  */
 281 #define CONFIG_STACKSIZE                (30 * 1024)
 282
 283 #define CONFIG_SYS_INIT_SP_OFFSET \
 284         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 285 #define CONFIG_SYS_INIT_SP_ADDR \
 286         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 287
 288 #ifdef CONFIG_SPL_BUILD
 289 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 290 #else
 291 /* start of monitor */
 292 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 293 #endif
 294
 295 #define CONFIG_SYS_QE_FW_ADDR   0x67f40000
 296
 297 /*
 298  * Environment
 299  */
 300
 301 #define CONFIG_ENV_OVERWRITE
 302
 303 #if defined(CONFIG_SD_BOOT)
 304 #define CONFIG_ENV_OFFSET               0x100000
 305 #define CONFIG_ENV_IS_IN_MMC
 306 #define CONFIG_SYS_MMC_ENV_DEV  0
 307 #define CONFIG_ENV_SIZE                 0x2000
 308 #elif defined(CONFIG_QSPI_BOOT)
 309 #define CONFIG_ENV_IS_IN_SPI_FLASH
 310 #define CONFIG_ENV_SIZE                 0x2000
 311 #define CONFIG_ENV_OFFSET               0x100000
 312 #define CONFIG_ENV_SECT_SIZE    0x10000
 313 #endif
 314
 315 #define CONFIG_OF_BOARD_SETUP
 316 #define CONFIG_OF_STDOUT_VIA_ALIAS
 317 #define CONFIG_CMD_BOOTZ
 318
 319 #define CONFIG_MISC_INIT_R
 320
 321 /* Hash command with SHA acceleration supported in hardware */
 322
 323 #ifdef CONFIG_FSL_CAAM
 324
 325 #define CONFIG_CMD_HASH
 326
 327 #define CONFIG_SHA_HW_ACCEL
 328
 329 #endif
 330
 331 #include <asm/fsl_secure_boot.h>
 332
 333 #endif