]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/ls1021aqds.h
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
[people/ms/u-boot.git] / include / configs / ls1021aqds.h
1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_LS102XA
11
12 #define CONFIG_ARMV7_PSCI_1_0
13
14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
15
16 #define CONFIG_SYS_FSL_CLK
17
18 #define CONFIG_DISPLAY_CPUINFO
19 #define CONFIG_DISPLAY_BOARDINFO
20
21 #define CONFIG_SKIP_LOWLEVEL_INIT
22 #define CONFIG_BOARD_EARLY_INIT_F
23
24 #define CONFIG_DEEP_SLEEP
25 #if defined(CONFIG_DEEP_SLEEP)
26 #define CONFIG_SILENT_CONSOLE
27 #endif
28
29 /*
30 * Size of malloc() pool
31 */
32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
33
34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
36
37 /*
38 * Generic Timer Definitions
39 */
40 #define GENERIC_TIMER_CLK 12500000
41
42 #ifndef __ASSEMBLY__
43 unsigned long get_board_sys_clk(void);
44 unsigned long get_board_ddr_clk(void);
45 #endif
46
47 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
48 #define CONFIG_SYS_CLK_FREQ 100000000
49 #define CONFIG_DDR_CLK_FREQ 100000000
50 #define CONFIG_QIXIS_I2C_ACCESS
51 #else
52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
53 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
54 #endif
55
56 #ifdef CONFIG_RAMBOOT_PBL
57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
58 #endif
59
60 #ifdef CONFIG_SD_BOOT
61 #ifdef CONFIG_SD_BOOT_QSPI
62 #define CONFIG_SYS_FSL_PBL_RCW \
63 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
64 #else
65 #define CONFIG_SYS_FSL_PBL_RCW \
66 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
67 #endif
68 #define CONFIG_SPL_FRAMEWORK
69 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
70 #define CONFIG_SPL_LIBCOMMON_SUPPORT
71 #define CONFIG_SPL_LIBGENERIC_SUPPORT
72 #define CONFIG_SPL_ENV_SUPPORT
73 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
74 #define CONFIG_SPL_I2C_SUPPORT
75 #define CONFIG_SPL_WATCHDOG_SUPPORT
76 #define CONFIG_SPL_SERIAL_SUPPORT
77 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
78 #define CONFIG_SPL_MMC_SUPPORT
79 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
80 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600
81
82 #define CONFIG_SPL_TEXT_BASE 0x10000000
83 #define CONFIG_SPL_MAX_SIZE 0x1a000
84 #define CONFIG_SPL_STACK 0x1001d000
85 #define CONFIG_SPL_PAD_TO 0x1c000
86 #define CONFIG_SYS_TEXT_BASE 0x82000000
87
88 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
89 CONFIG_SYS_MONITOR_LEN)
90 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
91 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
92 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
93 #define CONFIG_SYS_MONITOR_LEN 0xc0000
94 #endif
95
96 #ifdef CONFIG_QSPI_BOOT
97 #define CONFIG_SYS_TEXT_BASE 0x40010000
98 #endif
99
100 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
101 #define CONFIG_SYS_NO_FLASH
102 #endif
103
104 #ifdef CONFIG_NAND_BOOT
105 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
106 #define CONFIG_SPL_FRAMEWORK
107 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
108 #define CONFIG_SPL_LIBCOMMON_SUPPORT
109 #define CONFIG_SPL_LIBGENERIC_SUPPORT
110 #define CONFIG_SPL_ENV_SUPPORT
111 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
112 #define CONFIG_SPL_I2C_SUPPORT
113 #define CONFIG_SPL_WATCHDOG_SUPPORT
114 #define CONFIG_SPL_SERIAL_SUPPORT
115 #define CONFIG_SPL_NAND_SUPPORT
116 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
117
118 #define CONFIG_SPL_TEXT_BASE 0x10000000
119 #define CONFIG_SPL_MAX_SIZE 0x1a000
120 #define CONFIG_SPL_STACK 0x1001d000
121 #define CONFIG_SPL_PAD_TO 0x1c000
122 #define CONFIG_SYS_TEXT_BASE 0x82000000
123
124 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
125 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
126 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
127 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
128 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
129
130 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
131 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
132 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
133 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
134 #define CONFIG_SYS_MONITOR_LEN 0x80000
135 #endif
136
137 #ifndef CONFIG_SYS_TEXT_BASE
138 #define CONFIG_SYS_TEXT_BASE 0x60100000
139 #endif
140
141 #define CONFIG_NR_DRAM_BANKS 1
142
143 #define CONFIG_DDR_SPD
144 #define SPD_EEPROM_ADDRESS 0x51
145 #define CONFIG_SYS_SPD_BUS_NUM 0
146
147 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
148 #ifndef CONFIG_SYS_FSL_DDR4
149 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
150 #define CONFIG_SYS_DDR_RAW_TIMING
151 #endif
152 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
153 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
154
155 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
156 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
157
158 #define CONFIG_DDR_ECC
159 #ifdef CONFIG_DDR_ECC
160 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
161 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
162 #endif
163
164 #define CONFIG_SYS_HAS_SERDES
165
166 #define CONFIG_FSL_CAAM /* Enable CAAM */
167
168 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
169 !defined(CONFIG_QSPI_BOOT)
170 #define CONFIG_U_QE
171 #endif
172
173 /*
174 * IFC Definitions
175 */
176 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
177 #define CONFIG_FSL_IFC
178 #define CONFIG_SYS_FLASH_BASE 0x60000000
179 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
180
181 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
182 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
183 CSPR_PORT_SIZE_16 | \
184 CSPR_MSEL_NOR | \
185 CSPR_V)
186 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
187 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
188 + 0x8000000) | \
189 CSPR_PORT_SIZE_16 | \
190 CSPR_MSEL_NOR | \
191 CSPR_V)
192 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
193
194 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
195 CSOR_NOR_TRHZ_80)
196 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
197 FTIM0_NOR_TEADC(0x5) | \
198 FTIM0_NOR_TEAHC(0x5))
199 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
200 FTIM1_NOR_TRAD_NOR(0x1a) | \
201 FTIM1_NOR_TSEQRAD_NOR(0x13))
202 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
203 FTIM2_NOR_TCH(0x4) | \
204 FTIM2_NOR_TWPH(0xe) | \
205 FTIM2_NOR_TWP(0x1c))
206 #define CONFIG_SYS_NOR_FTIM3 0
207
208 #define CONFIG_FLASH_CFI_DRIVER
209 #define CONFIG_SYS_FLASH_CFI
210 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
211 #define CONFIG_SYS_FLASH_QUIET_TEST
212 #define CONFIG_FLASH_SHOW_PROGRESS 45
213 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
214 #define CONFIG_SYS_WRITE_SWAPPED_DATA
215
216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
217 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
218 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
220
221 #define CONFIG_SYS_FLASH_EMPTY_INFO
222 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
223 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
224
225 /*
226 * NAND Flash Definitions
227 */
228 #define CONFIG_NAND_FSL_IFC
229
230 #define CONFIG_SYS_NAND_BASE 0x7e800000
231 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
232
233 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
234
235 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
236 | CSPR_PORT_SIZE_8 \
237 | CSPR_MSEL_NAND \
238 | CSPR_V)
239 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
240 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
241 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
242 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
243 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
244 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
245 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
246 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
247
248 #define CONFIG_SYS_NAND_ONFI_DETECTION
249
250 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
251 FTIM0_NAND_TWP(0x18) | \
252 FTIM0_NAND_TWCHT(0x7) | \
253 FTIM0_NAND_TWH(0xa))
254 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
255 FTIM1_NAND_TWBE(0x39) | \
256 FTIM1_NAND_TRR(0xe) | \
257 FTIM1_NAND_TRP(0x18))
258 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
259 FTIM2_NAND_TREH(0xa) | \
260 FTIM2_NAND_TWHRE(0x1e))
261 #define CONFIG_SYS_NAND_FTIM3 0x0
262
263 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
264 #define CONFIG_SYS_MAX_NAND_DEVICE 1
265 #define CONFIG_CMD_NAND
266
267 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
268 #endif
269
270 /*
271 * QIXIS Definitions
272 */
273 #define CONFIG_FSL_QIXIS
274
275 #ifdef CONFIG_FSL_QIXIS
276 #define QIXIS_BASE 0x7fb00000
277 #define QIXIS_BASE_PHYS QIXIS_BASE
278 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
279 #define QIXIS_LBMAP_SWITCH 6
280 #define QIXIS_LBMAP_MASK 0x0f
281 #define QIXIS_LBMAP_SHIFT 0
282 #define QIXIS_LBMAP_DFLTBANK 0x00
283 #define QIXIS_LBMAP_ALTBANK 0x04
284 #define QIXIS_PWR_CTL 0x21
285 #define QIXIS_PWR_CTL_POWEROFF 0x80
286 #define QIXIS_RST_CTL_RESET 0x44
287 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
288 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
289 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
290
291 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
292 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
293 CSPR_PORT_SIZE_8 | \
294 CSPR_MSEL_GPCM | \
295 CSPR_V)
296 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
297 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
298 CSOR_NOR_NOR_MODE_AVD_NOR | \
299 CSOR_NOR_TRHZ_80)
300
301 /*
302 * QIXIS Timing parameters for IFC GPCM
303 */
304 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
305 FTIM0_GPCM_TEADC(0xe) | \
306 FTIM0_GPCM_TEAHC(0xe))
307 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
308 FTIM1_GPCM_TRAD(0x1f))
309 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
310 FTIM2_GPCM_TCH(0xe) | \
311 FTIM2_GPCM_TWP(0xf0))
312 #define CONFIG_SYS_FPGA_FTIM3 0x0
313 #endif
314
315 #if defined(CONFIG_NAND_BOOT)
316 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
317 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
318 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
319 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
320 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
321 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
322 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
323 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
324 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
325 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
326 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
327 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
328 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
329 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
330 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
331 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
332 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
333 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
334 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
335 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
336 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
337 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
338 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
339 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
340 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
341 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
342 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
343 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
344 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
345 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
346 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
347 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
348 #else
349 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
357 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
358 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
359 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
360 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
361 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
362 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
363 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
364 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
365 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
366 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
367 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
368 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
369 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
370 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
371 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
372 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
373 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
374 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
375 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
376 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
377 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
378 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
379 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
380 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
381 #endif
382
383 /*
384 * Serial Port
385 */
386 #ifdef CONFIG_LPUART
387 #define CONFIG_LPUART_32B_REG
388 #else
389 #define CONFIG_CONS_INDEX 1
390 #define CONFIG_SYS_NS16550_SERIAL
391 #ifndef CONFIG_DM_SERIAL
392 #define CONFIG_SYS_NS16550_REG_SIZE 1
393 #endif
394 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
395 #endif
396
397 #define CONFIG_BAUDRATE 115200
398
399 /*
400 * I2C
401 */
402 #define CONFIG_SYS_I2C
403 #define CONFIG_SYS_I2C_MXC
404 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
405 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
406 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
407
408 /*
409 * I2C bus multiplexer
410 */
411 #define I2C_MUX_PCA_ADDR_PRI 0x77
412 #define I2C_MUX_CH_DEFAULT 0x8
413 #define I2C_MUX_CH_CH7301 0xC
414
415 /*
416 * MMC
417 */
418 #define CONFIG_MMC
419 #define CONFIG_FSL_ESDHC
420 #define CONFIG_GENERIC_MMC
421
422 #define CONFIG_DOS_PARTITION
423
424 /* SPI */
425 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
426 /* QSPI */
427 #define QSPI0_AMBA_BASE 0x40000000
428 #define FSL_QSPI_FLASH_SIZE (1 << 24)
429 #define FSL_QSPI_FLASH_NUM 2
430
431 /* DSPI */
432
433 /* DM SPI */
434 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
435 #define CONFIG_DM_SPI_FLASH
436 #define CONFIG_SPI_FLASH_DATAFLASH
437 #endif
438 #endif
439
440 /*
441 * USB
442 */
443 /* EHCI Support - disbaled by default */
444 /*#define CONFIG_HAS_FSL_DR_USB*/
445
446 #ifdef CONFIG_HAS_FSL_DR_USB
447 #define CONFIG_USB_EHCI
448 #define CONFIG_USB_EHCI_FSL
449 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
450 #endif
451
452 /*XHCI Support - enabled by default*/
453 #define CONFIG_HAS_FSL_XHCI_USB
454
455 #ifdef CONFIG_HAS_FSL_XHCI_USB
456 #define CONFIG_USB_XHCI_FSL
457 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
458 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
459 #endif
460
461 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
462 #define CONFIG_USB_STORAGE
463 #endif
464
465 /*
466 * Video
467 */
468 #define CONFIG_FSL_DCU_FB
469
470 #ifdef CONFIG_FSL_DCU_FB
471 #define CONFIG_VIDEO
472 #define CONFIG_CMD_BMP
473 #define CONFIG_CFB_CONSOLE
474 #define CONFIG_VGA_AS_SINGLE_DEVICE
475 #define CONFIG_VIDEO_LOGO
476 #define CONFIG_VIDEO_BMP_LOGO
477 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
478
479 #define CONFIG_FSL_DIU_CH7301
480 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
481 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
482 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
483 #endif
484
485 /*
486 * eTSEC
487 */
488 #define CONFIG_TSEC_ENET
489
490 #ifdef CONFIG_TSEC_ENET
491 #define CONFIG_MII
492 #define CONFIG_MII_DEFAULT_TSEC 3
493 #define CONFIG_TSEC1 1
494 #define CONFIG_TSEC1_NAME "eTSEC1"
495 #define CONFIG_TSEC2 1
496 #define CONFIG_TSEC2_NAME "eTSEC2"
497 #define CONFIG_TSEC3 1
498 #define CONFIG_TSEC3_NAME "eTSEC3"
499
500 #define TSEC1_PHY_ADDR 1
501 #define TSEC2_PHY_ADDR 2
502 #define TSEC3_PHY_ADDR 3
503
504 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
505 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
506 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
507
508 #define TSEC1_PHYIDX 0
509 #define TSEC2_PHYIDX 0
510 #define TSEC3_PHYIDX 0
511
512 #define CONFIG_ETHPRIME "eTSEC1"
513
514 #define CONFIG_PHY_GIGE
515 #define CONFIG_PHYLIB
516 #define CONFIG_PHY_REALTEK
517
518 #define CONFIG_HAS_ETH0
519 #define CONFIG_HAS_ETH1
520 #define CONFIG_HAS_ETH2
521
522 #define CONFIG_FSL_SGMII_RISER 1
523 #define SGMII_RISER_PHY_OFFSET 0x1b
524
525 #ifdef CONFIG_FSL_SGMII_RISER
526 #define CONFIG_SYS_TBIPA_VALUE 8
527 #endif
528
529 #endif
530
531 /* PCIe */
532 #define CONFIG_PCI /* Enable PCI/PCIE */
533 #define CONFIG_PCIE1 /* PCIE controller 1 */
534 #define CONFIG_PCIE2 /* PCIE controller 2 */
535 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
536 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
537
538 #define CONFIG_SYS_PCI_64BIT
539
540 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
541 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
542 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
543 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
544
545 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
546 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
547 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
548
549 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
550 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
551 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
552
553 #ifdef CONFIG_PCI
554 #define CONFIG_PCI_PNP
555 #define CONFIG_PCI_SCAN_SHOW
556 #define CONFIG_CMD_PCI
557 #endif
558
559 #define CONFIG_CMDLINE_TAG
560 #define CONFIG_CMDLINE_EDITING
561
562 #define CONFIG_ARMV7_NONSEC
563 #define CONFIG_ARMV7_VIRT
564 #define CONFIG_PEN_ADDR_BIG_ENDIAN
565 #define CONFIG_LAYERSCAPE_NS_ACCESS
566 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
567 #define CONFIG_TIMER_CLK_FREQ 12500000
568
569 #define CONFIG_HWCONFIG
570 #define HWCONFIG_BUFFER_SIZE 256
571
572 #define CONFIG_FSL_DEVICE_DISABLE
573
574
575 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000
576
577 #ifdef CONFIG_LPUART
578 #define CONFIG_EXTRA_ENV_SETTINGS \
579 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
580 "fdt_high=0xffffffff\0" \
581 "initrd_high=0xffffffff\0" \
582 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
583 #else
584 #define CONFIG_EXTRA_ENV_SETTINGS \
585 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
586 "fdt_high=0xffffffff\0" \
587 "initrd_high=0xffffffff\0" \
588 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
589 #endif
590
591 /*
592 * Miscellaneous configurable options
593 */
594 #define CONFIG_SYS_LONGHELP /* undef to save memory */
595 #define CONFIG_AUTO_COMPLETE
596 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
597 #define CONFIG_SYS_PBSIZE \
598 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
599 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
600 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
601
602 #define CONFIG_SYS_MEMTEST_START 0x80000000
603 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
604
605 #define CONFIG_SYS_LOAD_ADDR 0x82000000
606
607 #define CONFIG_LS102XA_STREAM_ID
608
609 /*
610 * Stack sizes
611 * The stack sizes are set up in start.S using the settings below
612 */
613 #define CONFIG_STACKSIZE (30 * 1024)
614
615 #define CONFIG_SYS_INIT_SP_OFFSET \
616 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
617 #define CONFIG_SYS_INIT_SP_ADDR \
618 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
619
620 #ifdef CONFIG_SPL_BUILD
621 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
622 #else
623 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
624 #endif
625
626 /*
627 * Environment
628 */
629 #define CONFIG_ENV_OVERWRITE
630
631 #if defined(CONFIG_SD_BOOT)
632 #define CONFIG_ENV_OFFSET 0x100000
633 #define CONFIG_ENV_IS_IN_MMC
634 #define CONFIG_SYS_MMC_ENV_DEV 0
635 #define CONFIG_ENV_SIZE 0x2000
636 #elif defined(CONFIG_QSPI_BOOT)
637 #define CONFIG_ENV_IS_IN_SPI_FLASH
638 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
639 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
640 #define CONFIG_ENV_SECT_SIZE 0x10000
641 #elif defined(CONFIG_NAND_BOOT)
642 #define CONFIG_ENV_IS_IN_NAND
643 #define CONFIG_ENV_SIZE 0x2000
644 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
645 #else
646 #define CONFIG_ENV_IS_IN_FLASH
647 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
648 #define CONFIG_ENV_SIZE 0x2000
649 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
650 #endif
651
652 #define CONFIG_MISC_INIT_R
653
654 /* Hash command with SHA acceleration supported in hardware */
655 #ifdef CONFIG_FSL_CAAM
656 #define CONFIG_CMD_HASH
657 #define CONFIG_SHA_HW_ACCEL
658 #endif
659
660 #include <asm/fsl_secure_boot.h>
661 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
662
663 #endif