include/configs/ls1021aqds.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_LS102XA
  11
  12 #define CONFIG_ARMV7_PSCI_1_0
  13
  14 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  15
  16 #define CONFIG_SYS_FSL_CLK
  17
  18 #define CONFIG_DISPLAY_CPUINFO
  19 #define CONFIG_DISPLAY_BOARDINFO
  20
  21 #define CONFIG_SKIP_LOWLEVEL_INIT
  22 #define CONFIG_BOARD_EARLY_INIT_F
  23
  24 #define CONFIG_DEEP_SLEEP
  25 #if defined(CONFIG_DEEP_SLEEP)
  26 #define CONFIG_SILENT_CONSOLE
  27 #endif
  28
  29 /*
  30  * Size of malloc() pool
  31  */
  32 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  33
  34 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  35 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  36
  37 /*
  38  * Generic Timer Definitions
  39  */
  40 #define GENERIC_TIMER_CLK               12500000
  41
  42 #ifndef __ASSEMBLY__
  43 unsigned long get_board_sys_clk(void);
  44 unsigned long get_board_ddr_clk(void);
  45 #endif
  46
  47 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  48 #define CONFIG_SYS_CLK_FREQ             100000000
  49 #define CONFIG_DDR_CLK_FREQ             100000000
  50 #define CONFIG_QIXIS_I2C_ACCESS
  51 #else
  52 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  53 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  54 #endif
  55
  56 #ifdef CONFIG_RAMBOOT_PBL
  57 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  58 #endif
  59
  60 #ifdef CONFIG_SD_BOOT
  61 #ifdef CONFIG_SD_BOOT_QSPI
  62 #define CONFIG_SYS_FSL_PBL_RCW  \
  63         board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
  64 #else
  65 #define CONFIG_SYS_FSL_PBL_RCW  \
  66         board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
  67 #endif
  68 #define CONFIG_SPL_FRAMEWORK
  69 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  70 #define CONFIG_SPL_WATCHDOG_SUPPORT
  71 #define CONFIG_SPL_SERIAL_SUPPORT
  72 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
  73 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x600
  74
  75 #define CONFIG_SPL_TEXT_BASE            0x10000000
  76 #define CONFIG_SPL_MAX_SIZE             0x1a000
  77 #define CONFIG_SPL_STACK                0x1001d000
  78 #define CONFIG_SPL_PAD_TO               0x1c000
  79 #define CONFIG_SYS_TEXT_BASE            0x82000000
  80
  81 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  82                 CONFIG_SYS_MONITOR_LEN)
  83 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  84 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  85 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  86 #define CONFIG_SYS_MONITOR_LEN          0xc0000
  87 #endif
  88
  89 #ifdef CONFIG_QSPI_BOOT
  90 #define CONFIG_SYS_TEXT_BASE            0x40010000
  91 #endif
  92
  93 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  94 #define CONFIG_SYS_NO_FLASH
  95 #endif
  96
  97 #ifdef CONFIG_NAND_BOOT
  98 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
  99 #define CONFIG_SPL_FRAMEWORK
 100 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
 101 #define CONFIG_SPL_WATCHDOG_SUPPORT
 102 #define CONFIG_SPL_SERIAL_SUPPORT
 103 #define CONFIG_SPL_NAND_SUPPORT
 104
 105 #define CONFIG_SPL_TEXT_BASE            0x10000000
 106 #define CONFIG_SPL_MAX_SIZE             0x1a000
 107 #define CONFIG_SPL_STACK                0x1001d000
 108 #define CONFIG_SPL_PAD_TO               0x1c000
 109 #define CONFIG_SYS_TEXT_BASE            0x82000000
 110
 111 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (400 << 10)
 112 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 113 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 114 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 115 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 116
 117 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 118 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 119 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 120 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 121 #define CONFIG_SYS_MONITOR_LEN          0x80000
 122 #endif
 123
 124 #ifndef CONFIG_SYS_TEXT_BASE
 125 #define CONFIG_SYS_TEXT_BASE            0x60100000
 126 #endif
 127
 128 #define CONFIG_NR_DRAM_BANKS            1
 129
 130 #define CONFIG_DDR_SPD
 131 #define SPD_EEPROM_ADDRESS              0x51
 132 #define CONFIG_SYS_SPD_BUS_NUM          0
 133
 134 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
 135 #ifndef CONFIG_SYS_FSL_DDR4
 136 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
 137 #define CONFIG_SYS_DDR_RAW_TIMING
 138 #endif
 139 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 140 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 141
 142 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
 143 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 144
 145 #define CONFIG_DDR_ECC
 146 #ifdef CONFIG_DDR_ECC
 147 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 148 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 149 #endif
 150
 151 #define CONFIG_SYS_HAS_SERDES
 152
 153 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 154
 155 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 156         !defined(CONFIG_QSPI_BOOT)
 157 #define CONFIG_U_QE
 158 #endif
 159
 160 /*
 161  * IFC Definitions
 162  */
 163 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 164 #define CONFIG_FSL_IFC
 165 #define CONFIG_SYS_FLASH_BASE           0x60000000
 166 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 167
 168 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 169 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 170                                 CSPR_PORT_SIZE_16 | \
 171                                 CSPR_MSEL_NOR | \
 172                                 CSPR_V)
 173 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 174 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 175                                 + 0x8000000) | \
 176                                 CSPR_PORT_SIZE_16 | \
 177                                 CSPR_MSEL_NOR | \
 178                                 CSPR_V)
 179 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 180
 181 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 182                                         CSOR_NOR_TRHZ_80)
 183 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 184                                         FTIM0_NOR_TEADC(0x5) | \
 185                                         FTIM0_NOR_TEAHC(0x5))
 186 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 187                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 188                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 189 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 190                                         FTIM2_NOR_TCH(0x4) | \
 191                                         FTIM2_NOR_TWPH(0xe) | \
 192                                         FTIM2_NOR_TWP(0x1c))
 193 #define CONFIG_SYS_NOR_FTIM3            0
 194
 195 #define CONFIG_FLASH_CFI_DRIVER
 196 #define CONFIG_SYS_FLASH_CFI
 197 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 198 #define CONFIG_SYS_FLASH_QUIET_TEST
 199 #define CONFIG_FLASH_SHOW_PROGRESS      45
 200 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 201 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 202
 203 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 204 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 205 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 206 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 207
 208 #define CONFIG_SYS_FLASH_EMPTY_INFO
 209 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 210                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 211
 212 /*
 213  * NAND Flash Definitions
 214  */
 215 #define CONFIG_NAND_FSL_IFC
 216
 217 #define CONFIG_SYS_NAND_BASE            0x7e800000
 218 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 219
 220 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 221
 222 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 223                                 | CSPR_PORT_SIZE_8      \
 224                                 | CSPR_MSEL_NAND        \
 225                                 | CSPR_V)
 226 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 227 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 228                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 229                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 230                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 231                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 232                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 233                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 234
 235 #define CONFIG_SYS_NAND_ONFI_DETECTION
 236
 237 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 238                                         FTIM0_NAND_TWP(0x18)   | \
 239                                         FTIM0_NAND_TWCHT(0x7) | \
 240                                         FTIM0_NAND_TWH(0xa))
 241 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 242                                         FTIM1_NAND_TWBE(0x39)  | \
 243                                         FTIM1_NAND_TRR(0xe)   | \
 244                                         FTIM1_NAND_TRP(0x18))
 245 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 246                                         FTIM2_NAND_TREH(0xa) | \
 247                                         FTIM2_NAND_TWHRE(0x1e))
 248 #define CONFIG_SYS_NAND_FTIM3           0x0
 249
 250 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 251 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 252 #define CONFIG_CMD_NAND
 253
 254 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 255 #endif
 256
 257 /*
 258  * QIXIS Definitions
 259  */
 260 #define CONFIG_FSL_QIXIS
 261
 262 #ifdef CONFIG_FSL_QIXIS
 263 #define QIXIS_BASE                      0x7fb00000
 264 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 265 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 266 #define QIXIS_LBMAP_SWITCH              6
 267 #define QIXIS_LBMAP_MASK                0x0f
 268 #define QIXIS_LBMAP_SHIFT               0
 269 #define QIXIS_LBMAP_DFLTBANK            0x00
 270 #define QIXIS_LBMAP_ALTBANK             0x04
 271 #define QIXIS_PWR_CTL                   0x21
 272 #define QIXIS_PWR_CTL_POWEROFF          0x80
 273 #define QIXIS_RST_CTL_RESET             0x44
 274 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 275 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 276 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 277
 278 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 279 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 280                                         CSPR_PORT_SIZE_8 | \
 281                                         CSPR_MSEL_GPCM | \
 282                                         CSPR_V)
 283 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 284 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 285                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 286                                         CSOR_NOR_TRHZ_80)
 287
 288 /*
 289  * QIXIS Timing parameters for IFC GPCM
 290  */
 291 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 292                                         FTIM0_GPCM_TEADC(0xe) | \
 293                                         FTIM0_GPCM_TEAHC(0xe))
 294 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 295                                         FTIM1_GPCM_TRAD(0x1f))
 296 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 297                                         FTIM2_GPCM_TCH(0xe) | \
 298                                         FTIM2_GPCM_TWP(0xf0))
 299 #define CONFIG_SYS_FPGA_FTIM3           0x0
 300 #endif
 301
 302 #if defined(CONFIG_NAND_BOOT)
 303 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 304 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 305 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 306 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 307 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 308 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 309 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 310 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 311 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 312 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 313 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 314 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 315 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 316 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 317 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 318 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 319 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 320 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 321 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 322 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 323 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 324 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 325 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 326 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 327 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 328 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 329 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 330 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 331 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 332 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 333 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 334 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 335 #else
 336 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 337 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 338 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 339 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 340 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 341 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 342 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 343 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 344 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 345 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 346 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 347 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 348 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 349 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 350 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 351 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 352 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 353 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 354 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 355 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 356 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 357 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 358 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 359 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 360 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 361 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 362 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 363 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 364 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 365 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 366 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 367 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 368 #endif
 369
 370 /*
 371  * Serial Port
 372  */
 373 #ifdef CONFIG_LPUART
 374 #define CONFIG_LPUART_32B_REG
 375 #else
 376 #define CONFIG_CONS_INDEX               1
 377 #define CONFIG_SYS_NS16550_SERIAL
 378 #ifndef CONFIG_DM_SERIAL
 379 #define CONFIG_SYS_NS16550_REG_SIZE     1
 380 #endif
 381 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 382 #endif
 383
 384 #define CONFIG_BAUDRATE                 115200
 385
 386 /*
 387  * I2C
 388  */
 389 #define CONFIG_SYS_I2C
 390 #define CONFIG_SYS_I2C_MXC
 391 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 392 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 393 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 394
 395 /*
 396  * I2C bus multiplexer
 397  */
 398 #define I2C_MUX_PCA_ADDR_PRI            0x77
 399 #define I2C_MUX_CH_DEFAULT              0x8
 400 #define I2C_MUX_CH_CH7301               0xC
 401
 402 /*
 403  * MMC
 404  */
 405 #define CONFIG_MMC
 406 #define CONFIG_FSL_ESDHC
 407 #define CONFIG_GENERIC_MMC
 408
 409 #define CONFIG_DOS_PARTITION
 410
 411 /* SPI */
 412 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 413 /* QSPI */
 414 #define QSPI0_AMBA_BASE                 0x40000000
 415 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 416 #define FSL_QSPI_FLASH_NUM              2
 417
 418 /* DSPI */
 419
 420 /* DM SPI */
 421 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 422 #define CONFIG_DM_SPI_FLASH
 423 #define CONFIG_SPI_FLASH_DATAFLASH
 424 #endif
 425 #endif
 426
 427 /*
 428  * USB
 429  */
 430 /* EHCI Support - disbaled by default */
 431 /*#define CONFIG_HAS_FSL_DR_USB*/
 432
 433 #ifdef CONFIG_HAS_FSL_DR_USB
 434 #define CONFIG_USB_EHCI
 435 #define CONFIG_USB_EHCI_FSL
 436 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 437 #endif
 438
 439 /*XHCI Support - enabled by default*/
 440 #define CONFIG_HAS_FSL_XHCI_USB
 441
 442 #ifdef CONFIG_HAS_FSL_XHCI_USB
 443 #define CONFIG_USB_XHCI_FSL
 444 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 445 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 446 #endif
 447
 448 /*
 449  * Video
 450  */
 451 #define CONFIG_FSL_DCU_FB
 452
 453 #ifdef CONFIG_FSL_DCU_FB
 454 #define CONFIG_VIDEO
 455 #define CONFIG_CMD_BMP
 456 #define CONFIG_CFB_CONSOLE
 457 #define CONFIG_VGA_AS_SINGLE_DEVICE
 458 #define CONFIG_VIDEO_LOGO
 459 #define CONFIG_VIDEO_BMP_LOGO
 460 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 461
 462 #define CONFIG_FSL_DIU_CH7301
 463 #define CONFIG_SYS_I2C_DVI_BUS_NUM      0
 464 #define CONFIG_SYS_I2C_QIXIS_ADDR       0x66
 465 #define CONFIG_SYS_I2C_DVI_ADDR         0x75
 466 #endif
 467
 468 /*
 469  * eTSEC
 470  */
 471 #define CONFIG_TSEC_ENET
 472
 473 #ifdef CONFIG_TSEC_ENET
 474 #define CONFIG_MII
 475 #define CONFIG_MII_DEFAULT_TSEC         3
 476 #define CONFIG_TSEC1                    1
 477 #define CONFIG_TSEC1_NAME               "eTSEC1"
 478 #define CONFIG_TSEC2                    1
 479 #define CONFIG_TSEC2_NAME               "eTSEC2"
 480 #define CONFIG_TSEC3                    1
 481 #define CONFIG_TSEC3_NAME               "eTSEC3"
 482
 483 #define TSEC1_PHY_ADDR                  1
 484 #define TSEC2_PHY_ADDR                  2
 485 #define TSEC3_PHY_ADDR                  3
 486
 487 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 488 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 489 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 490
 491 #define TSEC1_PHYIDX                    0
 492 #define TSEC2_PHYIDX                    0
 493 #define TSEC3_PHYIDX                    0
 494
 495 #define CONFIG_ETHPRIME                 "eTSEC1"
 496
 497 #define CONFIG_PHY_GIGE
 498 #define CONFIG_PHYLIB
 499 #define CONFIG_PHY_REALTEK
 500
 501 #define CONFIG_HAS_ETH0
 502 #define CONFIG_HAS_ETH1
 503 #define CONFIG_HAS_ETH2
 504
 505 #define CONFIG_FSL_SGMII_RISER          1
 506 #define SGMII_RISER_PHY_OFFSET          0x1b
 507
 508 #ifdef CONFIG_FSL_SGMII_RISER
 509 #define CONFIG_SYS_TBIPA_VALUE          8
 510 #endif
 511
 512 #endif
 513
 514 /* PCIe */
 515 #define CONFIG_PCI              /* Enable PCI/PCIE */
 516 #define CONFIG_PCIE1            /* PCIE controller 1 */
 517 #define CONFIG_PCIE2            /* PCIE controller 2 */
 518 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 519 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 520
 521 #define CONFIG_SYS_PCI_64BIT
 522
 523 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 524 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 525 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 526 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 527
 528 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 529 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 530 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 531
 532 #define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
 533 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
 534 #define CONFIG_SYS_PCIE_MEM_SIZE        0x08000000      /* 128M */
 535
 536 #ifdef CONFIG_PCI
 537 #define CONFIG_PCI_PNP
 538 #define CONFIG_PCI_SCAN_SHOW
 539 #define CONFIG_CMD_PCI
 540 #endif
 541
 542 #define CONFIG_CMDLINE_TAG
 543 #define CONFIG_CMDLINE_EDITING
 544
 545 #define CONFIG_ARMV7_NONSEC
 546 #define CONFIG_ARMV7_VIRT
 547 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 548 #define CONFIG_LAYERSCAPE_NS_ACCESS
 549 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 550 #define CONFIG_TIMER_CLK_FREQ           12500000
 551
 552 #define CONFIG_HWCONFIG
 553 #define HWCONFIG_BUFFER_SIZE            256
 554
 555 #define CONFIG_FSL_DEVICE_DISABLE
 556
 557
 558 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 559
 560 #ifdef CONFIG_LPUART
 561 #define CONFIG_EXTRA_ENV_SETTINGS       \
 562         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 563         "fdt_high=0xffffffff\0"         \
 564         "initrd_high=0xffffffff\0"      \
 565         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 566 #else
 567 #define CONFIG_EXTRA_ENV_SETTINGS       \
 568         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 569         "fdt_high=0xffffffff\0"         \
 570         "initrd_high=0xffffffff\0"      \
 571         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 572 #endif
 573
 574 /*
 575  * Miscellaneous configurable options
 576  */
 577 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 578 #define CONFIG_AUTO_COMPLETE
 579 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 580 #define CONFIG_SYS_PBSIZE               \
 581                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 582 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 583 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 584
 585 #define CONFIG_SYS_MEMTEST_START        0x80000000
 586 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 587
 588 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 589
 590 #define CONFIG_LS102XA_STREAM_ID
 591
 592 /*
 593  * Stack sizes
 594  * The stack sizes are set up in start.S using the settings below
 595  */
 596 #define CONFIG_STACKSIZE                (30 * 1024)
 597
 598 #define CONFIG_SYS_INIT_SP_OFFSET \
 599         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 600 #define CONFIG_SYS_INIT_SP_ADDR \
 601         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 602
 603 #ifdef CONFIG_SPL_BUILD
 604 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 605 #else
 606 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 607 #endif
 608
 609 /*
 610  * Environment
 611  */
 612 #define CONFIG_ENV_OVERWRITE
 613
 614 #if defined(CONFIG_SD_BOOT)
 615 #define CONFIG_ENV_OFFSET               0x100000
 616 #define CONFIG_ENV_IS_IN_MMC
 617 #define CONFIG_SYS_MMC_ENV_DEV          0
 618 #define CONFIG_ENV_SIZE                 0x2000
 619 #elif defined(CONFIG_QSPI_BOOT)
 620 #define CONFIG_ENV_IS_IN_SPI_FLASH
 621 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 622 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 623 #define CONFIG_ENV_SECT_SIZE            0x10000
 624 #elif defined(CONFIG_NAND_BOOT)
 625 #define CONFIG_ENV_IS_IN_NAND
 626 #define CONFIG_ENV_SIZE                 0x2000
 627 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 628 #else
 629 #define CONFIG_ENV_IS_IN_FLASH
 630 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 631 #define CONFIG_ENV_SIZE                 0x2000
 632 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 633 #endif
 634
 635 #define CONFIG_MISC_INIT_R
 636
 637 /* Hash command with SHA acceleration supported in hardware */
 638 #ifdef CONFIG_FSL_CAAM
 639 #define CONFIG_CMD_HASH
 640 #define CONFIG_SHA_HW_ACCEL
 641 #endif
 642
 643 #include <asm/fsl_secure_boot.h>
 644 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 645
 646 #endif