arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE support

[people/ms/u-boot.git] / include / configs / ls1021atwr.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <config_cmd_default.h>

#define CONFIG_LS102XA

#define CONFIG_SYS_GENERIC_BOARD

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE

/*
 * Generic Timer Definitions
 */
#define GENERIC_TIMER_CLK               12500000

#define CONFIG_SYS_CLK_FREQ             100000000
#define CONFIG_DDR_CLK_FREQ             100000000

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400

#define CONFIG_SPL_TEXT_BASE            0x10000000
#define CONFIG_SPL_MAX_SIZE             0x1a000
#define CONFIG_SPL_STACK                0x1001d000
#define CONFIG_SPL_PAD_TO               0x1c000
#define CONFIG_SYS_TEXT_BASE            0x82000000

#define CONFIG_SYS_SPL_MALLOC_START     0x80200000
#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
#define CONFIG_SPL_BSS_START_ADDR       0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
#define CONFIG_SYS_MONITOR_LEN          0x80000
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE            0x67f80000
#endif

#define CONFIG_NR_DRAM_BANKS            1
#define PHYS_SDRAM                      0x80000000
#define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)

#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_SYS_HAS_SERDES

#define CONFIG_FSL_CAAM                 /* Enable CAAM */

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
        !defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif

/*
 * IFC Definitions
 */
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE           0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
#define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
                                CSPR_PORT_SIZE_16 | \
                                CSPR_MSEL_NOR | \
                                CSPR_V)
#define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)

/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
                                        CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
                                        FTIM0_NOR_TEADC(0x5) | \
                                        FTIM0_NOR_TAVDS(0x0) | \
                                        FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
                                        FTIM1_NOR_TRAD_NOR(0x1A) | \
                                        FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
                                        FTIM2_NOR_TCH(0x4) | \
                                        FTIM2_NOR_TWP(0x1c) | \
                                        FTIM2_NOR_TWPH(0x0e))
#define CONFIG_SYS_NOR_FTIM3            0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

/* CPLD */

#define CONFIG_SYS_CPLD_BASE    0x7fb00000
#define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
#define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
                                        CSPR_PORT_SIZE_8 | \
                                        CSPR_MSEL_GPCM | \
                                        CSPR_V)
#define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
                                        CSOR_NOR_NOR_MODE_AVD_NOR | \
                                        CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
                                        FTIM0_GPCM_TEADC(0xf) | \
                                        FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
                                        FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
                                        FTIM2_GPCM_TCH(0xf) | \
                                        FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3           0x0
#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX               1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE     1
#define CONFIG_SYS_NS16550_CLK          get_serial_clock()

#define CONFIG_BAUDRATE                 115200

/*
 * I2C
 */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC

/* EEPROM */
#ifndef CONFIG_SD_BOOT
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM               1
#define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
#endif

/*
 * MMC
 */
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC

#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/*
 * Video
 */
#define CONFIG_FSL_DCU_FB

#ifdef CONFIG_FSL_DCU_FB
#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM      1
#define CONFIG_SYS_I2C_DVI_ADDR         0x39
#endif

/*
 * eTSEC
 */
#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC         1
#define CONFIG_TSEC1                    1
#define CONFIG_TSEC1_NAME               "eTSEC1"
#define CONFIG_TSEC2                    1
#define CONFIG_TSEC2_NAME               "eTSEC2"
#define CONFIG_TSEC3                    1
#define CONFIG_TSEC3_NAME               "eTSEC3"

#define TSEC1_PHY_ADDR                  2
#define TSEC2_PHY_ADDR                  0
#define TSEC3_PHY_ADDR                  1

#define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX                    0
#define TSEC2_PHYIDX                    0
#define TSEC3_PHYIDX                    0

#define CONFIG_ETHPRIME                 "eTSEC1"

#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

/* PCIe */
#define CONFIG_PCI              /* Enable PCI/PCIE */
#define CONFIG_PCIE1            /* PCIE controler 1 */
#define CONFIG_PCIE2            /* PCIE controler 2 */
#define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET

#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING

#define CONFIG_CMD_IMLS

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE            128

#define CONFIG_BOOTDELAY                3

#define CONFIG_EXTRA_ENV_SETTINGS       \
        "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
        "initrd_high=0xcfffffff\0"      \
        "fdt_high=0xcfffffff\0"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP             /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE               \
                (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS              16      /* max number of command args */
#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE

#define CONFIG_CMD_ENV_EXISTS
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START        0x80000000
#define CONFIG_SYS_MEMTEST_END          0x9fffffff

#define CONFIG_SYS_LOAD_ADDR            0x82000000

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE                (30 * 1024)

#define CONFIG_SYS_INIT_SP_OFFSET \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

#define CONFIG_SYS_QE_FW_ADDR     0x67f40000

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET               0x100000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV          0
#define CONFIG_ENV_SIZE                 0x20000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE                 0x20000
#define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
#endif

#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMD_BOOTZ

#define CONFIG_MISC_INIT_R

/* Hash command with SHA acceleration supported in hardware */
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CMD_BLOB
#endif

#endif