include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <config_cmd_default.h>
  11
  12 #define CONFIG_LS102XA
  13
  14 #define CONFIG_SYS_GENERIC_BOARD
  15
  16 #define CONFIG_DISPLAY_CPUINFO
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20 #define CONFIG_BOARD_EARLY_INIT_F
  21
  22 /*
  23  * Size of malloc() pool
  24  */
  25 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  26
  27 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  28 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  29
  30 /*
  31  * Generic Timer Definitions
  32  */
  33 #define GENERIC_TIMER_CLK               12500000
  34
  35 #define CONFIG_SYS_CLK_FREQ             100000000
  36 #define CONFIG_DDR_CLK_FREQ             100000000
  37
  38 #ifndef CONFIG_SYS_TEXT_BASE
  39 #define CONFIG_SYS_TEXT_BASE            0x67f80000
  40 #endif
  41
  42 #define CONFIG_NR_DRAM_BANKS            1
  43 #define PHYS_SDRAM                      0x80000000
  44 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
  45
  46 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
  47 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
  48
  49 #define CONFIG_SYS_HAS_SERDES
  50
  51 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
  52
  53 /*
  54  * IFC Definitions
  55  */
  56 #define CONFIG_FSL_IFC
  57 #define CONFIG_SYS_FLASH_BASE           0x60000000
  58 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  59
  60 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  61 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  62                                 CSPR_PORT_SIZE_16 | \
  63                                 CSPR_MSEL_NOR | \
  64                                 CSPR_V)
  65 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  66
  67 /* NOR Flash Timing Params */
  68 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
  69                                         CSOR_NOR_TRHZ_80)
  70 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
  71                                         FTIM0_NOR_TEADC(0x5) | \
  72                                         FTIM0_NOR_TAVDS(0x0) | \
  73                                         FTIM0_NOR_TEAHC(0x5))
  74 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
  75                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
  76                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
  77 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
  78                                         FTIM2_NOR_TCH(0x4) | \
  79                                         FTIM2_NOR_TWP(0x1c) | \
  80                                         FTIM2_NOR_TWPH(0x0e))
  81 #define CONFIG_SYS_NOR_FTIM3            0
  82
  83 #define CONFIG_FLASH_CFI_DRIVER
  84 #define CONFIG_SYS_FLASH_CFI
  85 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  86 #define CONFIG_SYS_FLASH_QUIET_TEST
  87 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
  88
  89 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  90 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  91 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  92 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  93
  94 #define CONFIG_SYS_FLASH_EMPTY_INFO
  95 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
  96
  97 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  98
  99 /* CPLD */
 100
 101 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 102 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 103
 104 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 105 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 106                                         CSPR_PORT_SIZE_8 | \
 107                                         CSPR_MSEL_GPCM | \
 108                                         CSPR_V)
 109 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 110 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 111                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 112                                         CSOR_NOR_TRHZ_80)
 113
 114 /* CPLD Timing parameters for IFC GPCM */
 115 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 116                                         FTIM0_GPCM_TEADC(0xf) | \
 117                                         FTIM0_GPCM_TEAHC(0xf))
 118 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 119                                         FTIM1_GPCM_TRAD(0x3f))
 120 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 121                                         FTIM2_GPCM_TCH(0xf) | \
 122                                         FTIM2_GPCM_TWP(0xff))
 123 #define CONFIG_SYS_FPGA_FTIM3           0x0
 124 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 125 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 126 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 127 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 128 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 129 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 130 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 131 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 132 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 133 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 134 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 135 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 136 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 137 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 138 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 139 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 140
 141 /*
 142  * Serial Port
 143  */
 144 #define CONFIG_CONS_INDEX               1
 145 #define CONFIG_SYS_NS16550
 146 #define CONFIG_SYS_NS16550_SERIAL
 147 #define CONFIG_SYS_NS16550_REG_SIZE     1
 148 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 149
 150 #define CONFIG_BAUDRATE                 115200
 151
 152 /*
 153  * I2C
 154  */
 155 #define CONFIG_CMD_I2C
 156 #define CONFIG_SYS_I2C
 157 #define CONFIG_SYS_I2C_MXC
 158
 159 /*
 160  * MMC
 161  */
 162 #define CONFIG_MMC
 163 #define CONFIG_CMD_MMC
 164 #define CONFIG_FSL_ESDHC
 165 #define CONFIG_GENERIC_MMC
 166
 167 /*
 168  * Video
 169  */
 170 #define CONFIG_FSL_DCU_FB
 171
 172 #ifdef CONFIG_FSL_DCU_FB
 173 #define CONFIG_VIDEO
 174 #define CONFIG_CMD_BMP
 175 #define CONFIG_CFB_CONSOLE
 176 #define CONFIG_VGA_AS_SINGLE_DEVICE
 177 #define CONFIG_VIDEO_LOGO
 178 #define CONFIG_VIDEO_BMP_LOGO
 179
 180 #define CONFIG_FSL_DCU_SII9022A
 181 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 182 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 183 #endif
 184
 185 /*
 186  * eTSEC
 187  */
 188 #define CONFIG_TSEC_ENET
 189
 190 #ifdef CONFIG_TSEC_ENET
 191 #define CONFIG_MII
 192 #define CONFIG_MII_DEFAULT_TSEC         1
 193 #define CONFIG_TSEC1                    1
 194 #define CONFIG_TSEC1_NAME               "eTSEC1"
 195 #define CONFIG_TSEC2                    1
 196 #define CONFIG_TSEC2_NAME               "eTSEC2"
 197 #define CONFIG_TSEC3                    1
 198 #define CONFIG_TSEC3_NAME               "eTSEC3"
 199
 200 #define TSEC1_PHY_ADDR                  2
 201 #define TSEC2_PHY_ADDR                  0
 202 #define TSEC3_PHY_ADDR                  1
 203
 204 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 205 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 206 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 207
 208 #define TSEC1_PHYIDX                    0
 209 #define TSEC2_PHYIDX                    0
 210 #define TSEC3_PHYIDX                    0
 211
 212 #define CONFIG_ETHPRIME                 "eTSEC1"
 213
 214 #define CONFIG_PHY_GIGE
 215 #define CONFIG_PHYLIB
 216 #define CONFIG_PHY_ATHEROS
 217
 218 #define CONFIG_HAS_ETH0
 219 #define CONFIG_HAS_ETH1
 220 #define CONFIG_HAS_ETH2
 221 #endif
 222
 223 #define CONFIG_CMD_PING
 224 #define CONFIG_CMD_DHCP
 225 #define CONFIG_CMD_MII
 226 #define CONFIG_CMD_NET
 227
 228 #define CONFIG_CMDLINE_TAG
 229 #define CONFIG_CMDLINE_EDITING
 230 #define CONFIG_CMD_IMLS
 231
 232 #define CONFIG_HWCONFIG
 233 #define HWCONFIG_BUFFER_SIZE            128
 234
 235 #define CONFIG_BOOTDELAY                3
 236
 237 #define CONFIG_EXTRA_ENV_SETTINGS       \
 238         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 239         "initrd_high=0xcfffffff\0"      \
 240         "fdt_high=0xcfffffff\0"
 241
 242 /*
 243  * Miscellaneous configurable options
 244  */
 245 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 246 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 247 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 248 #define CONFIG_AUTO_COMPLETE
 249 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 250 #define CONFIG_SYS_PBSIZE               \
 251                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 252 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 253 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 254
 255 #define CONFIG_CMD_ENV_EXISTS
 256 #define CONFIG_CMD_GREPENV
 257 #define CONFIG_CMD_MEMINFO
 258 #define CONFIG_CMD_MEMTEST
 259 #define CONFIG_SYS_MEMTEST_START        0x80000000
 260 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 261
 262 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 263
 264 /*
 265  * Stack sizes
 266  * The stack sizes are set up in start.S using the settings below
 267  */
 268 #define CONFIG_STACKSIZE                (30 * 1024)
 269
 270 #define CONFIG_SYS_INIT_SP_OFFSET \
 271         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 272 #define CONFIG_SYS_INIT_SP_ADDR \
 273         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 274
 275 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 276
 277 /*
 278  * Environment
 279  */
 280 #define CONFIG_ENV_OVERWRITE
 281
 282 #define CONFIG_ENV_IS_IN_FLASH
 283 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 284 #define CONFIG_ENV_SIZE                 0x20000
 285 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 286
 287 #define CONFIG_OF_LIBFDT
 288 #define CONFIG_OF_BOARD_SETUP
 289 #define CONFIG_CMD_BOOTZ
 290
 291 #define CONFIG_MISC_INIT_R
 292
 293 /* Hash command with SHA acceleration supported in hardware */
 294 #define CONFIG_CMD_HASH
 295 #define CONFIG_SHA_HW_ACCEL
 296
 297 #ifdef CONFIG_SECURE_BOOT
 298 #define CONFIG_CMD_BLOB
 299 #endif
 300
 301 #endif