include/configs/ls1043a_common.h

   1 /*
   2  * Copyright (C) 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043A_COMMON_H
   8 #define __LS1043A_COMMON_H
   9
  10 #define CONFIG_REMAKE_ELF
  11 #define CONFIG_FSL_LAYERSCAPE
  12 #define CONFIG_FSL_LSCH2
  13 #define CONFIG_LS1043A
  14 #define CONFIG_MP
  15 #define CONFIG_SYS_FSL_CLK
  16 #define CONFIG_GICV2
  17
  18 #include <asm/arch/config.h>
  19 #ifdef CONFIG_SYS_FSL_SRDS_1
  20 #define CONFIG_SYS_HAS_SERDES
  21 #endif
  22
  23 /* Link Definitions */
  24 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  25
  26 #define CONFIG_SUPPORT_RAW_INITRD
  27
  28 #define CONFIG_SKIP_LOWLEVEL_INIT
  29 #define CONFIG_BOARD_EARLY_INIT_F       1
  30
  31 #ifndef CONFIG_SYS_FSL_DDR4
  32 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  33 #endif
  34
  35 #define CONFIG_VERY_BIG_RAM
  36 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000
  37 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  38 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  39 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
  40
  41 #define CPU_RELEASE_ADDR               secondary_boot_func
  42
  43 /* Generic Timer Definitions */
  44 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  45
  46 /* Size of malloc() pool */
  47 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 1024 * 1024)
  48
  49 /* Serial Port */
  50 #define CONFIG_CONS_INDEX               1
  51 #define CONFIG_SYS_NS16550_SERIAL
  52 #define CONFIG_SYS_NS16550_REG_SIZE     1
  53 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
  54
  55 #define CONFIG_BAUDRATE                 115200
  56 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  57
  58 /* SD boot SPL */
  59 #ifdef CONFIG_SD_BOOT
  60 #define CONFIG_SPL_FRAMEWORK
  61 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  62 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  63 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  64 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  65 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  66 #define CONFIG_SPL_WATCHDOG_SUPPORT
  67 #define CONFIG_SPL_SERIAL_SUPPORT
  68 #define CONFIG_SPL_MMC_SUPPORT
  69 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xf0
  70 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x500
  71
  72 #define CONFIG_SPL_TEXT_BASE            0x10000000
  73 #define CONFIG_SPL_MAX_SIZE             0x1d000
  74 #define CONFIG_SPL_STACK                0x1001e000
  75 #define CONFIG_SPL_PAD_TO               0x1d000
  76
  77 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
  78                                         CONFIG_SYS_MONITOR_LEN)
  79 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  80 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  81 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  82 #define CONFIG_SYS_MONITOR_LEN          0xa0000
  83 #endif
  84
  85 /* NAND SPL */
  86 #ifdef CONFIG_NAND_BOOT
  87 #define CONFIG_SPL_PBL_PAD
  88 #define CONFIG_SPL_FRAMEWORK
  89 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
  90 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  91 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  92 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  93 #define CONFIG_SPL_WATCHDOG_SUPPORT
  94 #define CONFIG_SPL_SERIAL_SUPPORT
  95 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  96 #define CONFIG_SPL_NAND_SUPPORT
  97 #define CONFIG_SPL_TEXT_BASE            0x10000000
  98 #define CONFIG_SPL_MAX_SIZE             0x1a000
  99 #define CONFIG_SPL_STACK                0x1001d000
 100 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 101 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 102 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 103 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 104 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 105 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 106 #define CONFIG_SYS_MONITOR_LEN          0xa0000
 107 #endif
 108
 109 /* IFC */
 110 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 111 #define CONFIG_FSL_IFC
 112 /*
 113  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 114  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 115  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 116  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 117  */
 118 #define CONFIG_SYS_FLASH_BASE                   0x60000000
 119 #define CONFIG_SYS_FLASH_BASE_PHYS              CONFIG_SYS_FLASH_BASE
 120 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 121
 122 #ifndef CONFIG_SYS_NO_FLASH
 123 #define CONFIG_FLASH_CFI_DRIVER
 124 #define CONFIG_SYS_FLASH_CFI
 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 126 #define CONFIG_SYS_FLASH_QUIET_TEST
 127 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 128 #endif
 129 #endif
 130
 131 /* I2C */
 132 #define CONFIG_SYS_I2C
 133 #define CONFIG_SYS_I2C_MXC
 134 #define CONFIG_SYS_I2C_MXC_I2C1
 135 #define CONFIG_SYS_I2C_MXC_I2C2
 136 #define CONFIG_SYS_I2C_MXC_I2C3
 137 #define CONFIG_SYS_I2C_MXC_I2C4
 138
 139 /* PCIe */
 140 #define CONFIG_PCI              /* Enable PCI/PCIE */
 141 #define CONFIG_PCIE1            /* PCIE controller 1 */
 142 #define CONFIG_PCIE2            /* PCIE controller 2 */
 143 #define CONFIG_PCIE3            /* PCIE controller 3 */
 144 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 145 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 146
 147 #define CONFIG_SYS_PCI_64BIT
 148
 149 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 150 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 151 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 152 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 153
 154 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 155 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 156 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 157
 158 #define CONFIG_SYS_PCIE_MEM_BUS         0x40000000
 159 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x40000000
 160 #define CONFIG_SYS_PCIE_MEM_SIZE        0x40000000      /* 1G */
 161
 162 #ifdef CONFIG_PCI
 163 #define CONFIG_NET_MULTI
 164 #define CONFIG_PCI_PNP
 165 #define CONFIG_E1000
 166 #define CONFIG_PCI_SCAN_SHOW
 167 #define CONFIG_CMD_PCI
 168 #endif
 169
 170 /* Command line configuration */
 171 #define CONFIG_CMD_ENV
 172 #define CONFIG_MENU
 173 #define CONFIG_CMD_PXE
 174
 175 /*  MMC  */
 176 #define CONFIG_MMC
 177 #ifdef CONFIG_MMC
 178 #define CONFIG_FSL_ESDHC
 179 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 180 #define CONFIG_GENERIC_MMC
 181 #define CONFIG_DOS_PARTITION
 182 #endif
 183
 184 /*  DSPI  */
 185 #define CONFIG_FSL_DSPI
 186 #ifdef CONFIG_FSL_DSPI
 187 #define CONFIG_DM_SPI_FLASH
 188 #define CONFIG_SPI_FLASH_STMICRO        /* cs0 */
 189 #define CONFIG_SPI_FLASH_SST            /* cs1 */
 190 #define CONFIG_SPI_FLASH_EON            /* cs2 */
 191 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 192 #define CONFIG_SF_DEFAULT_BUS           1
 193 #define CONFIG_SF_DEFAULT_CS            0
 194 #endif
 195 #endif
 196
 197 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
 198
 199 /* FMan ucode */
 200 #define CONFIG_SYS_DPAA_FMAN
 201 #ifdef CONFIG_SYS_DPAA_FMAN
 202 #define CONFIG_SYS_FM_MURAM_SIZE        0x60000
 203
 204 #ifdef CONFIG_NAND_BOOT
 205 /* Store Fman ucode at offeset 0x160000(11 blocks). */
 206 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 207 #define CONFIG_SYS_FMAN_FW_ADDR         (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 208 #elif defined(CONFIG_SD_BOOT)
 209 /*
 210  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 211  * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 212  * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
 213  */
 214 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 215 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 216 #elif defined(CONFIG_QSPI_BOOT)
 217 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 218 #define CONFIG_SYS_FMAN_FW_ADDR         0x400d0000
 219 #define CONFIG_ENV_SPI_BUS              0
 220 #define CONFIG_ENV_SPI_CS               0
 221 #define CONFIG_ENV_SPI_MAX_HZ           1000000
 222 #define CONFIG_ENV_SPI_MODE             0x03
 223 #else
 224 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 225 /* FMan fireware Pre-load address */
 226 #define CONFIG_SYS_FMAN_FW_ADDR         0x60300000
 227 #endif
 228 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 229 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 230 #endif
 231
 232 /* Miscellaneous configurable options */
 233 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 234 #define CONFIG_ARCH_EARLY_INIT_R
 235 #define CONFIG_BOARD_LATE_INIT
 236
 237 #define CONFIG_HWCONFIG
 238 #define HWCONFIG_BUFFER_SIZE            128
 239
 240 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 241 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
 242                         "5m(kernel),1m(dtb),9m(file_system)"
 243 #else
 244 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
 245                         "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
 246                         "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
 247                         "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
 248                         "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
 249                         "40m(nor_bank4_fit);7e800000.flash:" \
 250                         "1m(nand_uboot),1m(nand_uboot_env)," \
 251                         "20m(nand_fit);spi0.0:1m(uboot)," \
 252                         "5m(kernel),1m(dtb),9m(file_system)"
 253 #endif
 254
 255 /* Initial environment variables */
 256 #define CONFIG_EXTRA_ENV_SETTINGS               \
 257         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 258         "loadaddr=0x80100000\0"                 \
 259         "fdt_high=0xffffffffffffffff\0"         \
 260         "initrd_high=0xffffffffffffffff\0"      \
 261         "kernel_start=0x61100000\0"             \
 262         "kernel_load=0xa0000000\0"              \
 263         "kernel_size=0x2800000\0"               \
 264         "console=ttyS0,115200\0"                \
 265         "mtdparts=" MTDPARTS_DEFAULT "\0"
 266
 267 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 root=/dev/ram0 " \
 268                                         "earlycon=uart8250,mmio,0x21c0500 "    \
 269                                         MTDPARTS_DEFAULT
 270
 271 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 272 #define CONFIG_BOOTCOMMAND              "sf probe && sf read $kernel_load "    \
 273                                         "e0000 f00000 && bootm $kernel_load"
 274 #else
 275 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 276                                         "$kernel_size && bootm $kernel_load"
 277 #endif
 278
 279 /* Monitor Command Prompt */
 280 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 281 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 282                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 283 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 284 #define CONFIG_SYS_LONGHELP
 285 #define CONFIG_CMDLINE_EDITING          1
 286 #define CONFIG_AUTO_COMPLETE
 287 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 288
 289 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 290
 291 /* Hash command with SHA acceleration supported in hardware */
 292 #ifdef CONFIG_FSL_CAAM
 293 #define CONFIG_CMD_HASH
 294 #define CONFIG_SHA_HW_ACCEL
 295 #endif
 296
 297 #endif /* __LS1043A_COMMON_H */