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1 /*
2 * Copyright 2016 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __LS1046A_COMMON_H
8 #define __LS1046A_COMMON_H
9
10 /* SPL build */
11 #ifdef CONFIG_SPL_BUILD
12 #define SPL_NO_QBMAN
13 #define SPL_NO_FMAN
14 #define SPL_NO_ENV
15 #define SPL_NO_MISC
16 #define SPL_NO_QSPI
17 #define SPL_NO_USB
18 #define SPL_NO_SATA
19 #endif
20 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
21 #define SPL_NO_MMC
22 #endif
23 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
24 #define SPL_NO_IFC
25 #endif
26
27 #define CONFIG_REMAKE_ELF
28 #define CONFIG_FSL_LAYERSCAPE
29 #define CONFIG_MP
30 #define CONFIG_GICV2
31
32 #include <asm/arch/config.h>
33 #include <asm/arch/stream_id_lsch2.h>
34
35 /* Link Definitions */
36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
37
38 #define CONFIG_SUPPORT_RAW_INITRD
39
40 #define CONFIG_SKIP_LOWLEVEL_INIT
41
42 #define CONFIG_VERY_BIG_RAM
43 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
44 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
47
48 #define CPU_RELEASE_ADDR secondary_boot_func
49
50 /* Generic Timer Definitions */
51 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
52
53 /* Size of malloc() pool */
54 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
55
56 /* Serial Port */
57 #define CONFIG_CONS_INDEX 1
58 #define CONFIG_SYS_NS16550_SERIAL
59 #define CONFIG_SYS_NS16550_REG_SIZE 1
60 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
61
62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
63
64 /* SD boot SPL */
65 #ifdef CONFIG_SD_BOOT
66 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
67 #define CONFIG_SPL_LIBCOMMON_SUPPORT
68 #define CONFIG_SPL_LIBGENERIC_SUPPORT
69 #define CONFIG_SPL_ENV_SUPPORT
70 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
71 #define CONFIG_SPL_WATCHDOG_SUPPORT
72 #define CONFIG_SPL_I2C_SUPPORT
73 #define CONFIG_SPL_SERIAL_SUPPORT
74 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
75
76 #define CONFIG_SPL_MMC_SUPPORT
77 #define CONFIG_SPL_TEXT_BASE 0x10000000
78 #define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
79 #define CONFIG_SPL_STACK 0x10020000
80 #define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
81 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
83 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
84 CONFIG_SPL_BSS_MAX_SIZE)
85 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
86
87 #ifdef CONFIG_SECURE_BOOT
88 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
89 /*
90 * HDR would be appended at end of image and copied to DDR along
91 * with U-Boot image. Here u-boot max. size is 512K. So if binary
92 * size increases then increase this size in case of secure boot as
93 * it uses raw u-boot image instead of fit image.
94 */
95 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
96 #else
97 #define CONFIG_SYS_MONITOR_LEN 0x100000
98 #endif /* ifdef CONFIG_SECURE_BOOT */
99 #endif
100
101 /* NAND SPL */
102 #ifdef CONFIG_NAND_BOOT
103 #define CONFIG_SPL_PBL_PAD
104 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
105 #define CONFIG_SPL_LIBCOMMON_SUPPORT
106 #define CONFIG_SPL_LIBGENERIC_SUPPORT
107 #define CONFIG_SPL_ENV_SUPPORT
108 #define CONFIG_SPL_WATCHDOG_SUPPORT
109 #define CONFIG_SPL_I2C_SUPPORT
110 #define CONFIG_SPL_SERIAL_SUPPORT
111 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
112
113 #define CONFIG_SPL_NAND_SUPPORT
114 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
115 #define CONFIG_SPL_TEXT_BASE 0x10000000
116 #define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */
117 #define CONFIG_SPL_STACK 0x1001f000
118 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
119 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
120
121 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
122 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
123 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
124 CONFIG_SPL_BSS_MAX_SIZE)
125 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
126 #define CONFIG_SYS_MONITOR_LEN 0xa0000
127 #endif
128
129 /* I2C */
130 #define CONFIG_SYS_I2C
131 #define CONFIG_SYS_I2C_MXC
132 #define CONFIG_SYS_I2C_MXC_I2C1
133 #define CONFIG_SYS_I2C_MXC_I2C2
134 #define CONFIG_SYS_I2C_MXC_I2C3
135 #define CONFIG_SYS_I2C_MXC_I2C4
136
137 /* PCIe */
138 #define CONFIG_PCIE1 /* PCIE controller 1 */
139 #define CONFIG_PCIE2 /* PCIE controller 2 */
140 #define CONFIG_PCIE3 /* PCIE controller 3 */
141
142 #ifdef CONFIG_PCI
143 #define CONFIG_PCI_SCAN_SHOW
144 #endif
145
146 /* SATA */
147 #ifndef SPL_NO_SATA
148 #define CONFIG_SCSI_AHCI_PLAT
149
150 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
151
152 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
153 #define CONFIG_SYS_SCSI_MAX_LUN 1
154 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
155 CONFIG_SYS_SCSI_MAX_LUN)
156 #endif
157
158 /* Command line configuration */
159
160 /* MMC */
161 #ifndef SPL_NO_MMC
162 #ifdef CONFIG_MMC
163 #define CONFIG_FSL_ESDHC
164 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
165 #endif
166 #endif
167
168 /* FMan ucode */
169 #ifndef SPL_NO_FMAN
170 #define CONFIG_SYS_DPAA_FMAN
171 #ifdef CONFIG_SYS_DPAA_FMAN
172 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
173 #endif
174
175 #ifdef CONFIG_SD_BOOT
176 /*
177 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
178 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
179 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
180 */
181 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
182 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
183 #elif defined(CONFIG_QSPI_BOOT)
184 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
185 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
186 #define CONFIG_ENV_SPI_BUS 0
187 #define CONFIG_ENV_SPI_CS 0
188 #define CONFIG_ENV_SPI_MAX_HZ 1000000
189 #define CONFIG_ENV_SPI_MODE 0x03
190 #elif defined(CONFIG_NAND_BOOT)
191 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
192 #define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE)
193 #else
194 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
195 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
196 #endif
197 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
198 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
199 #endif
200
201 /* Miscellaneous configurable options */
202 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
203
204 #define CONFIG_HWCONFIG
205 #define HWCONFIG_BUFFER_SIZE 128
206
207 #include <config_distro_defaults.h>
208 #ifndef CONFIG_SPL_BUILD
209 #define BOOT_TARGET_DEVICES(func) \
210 func(SCSI, scsi, 0) \
211 func(MMC, mmc, 0) \
212 func(USB, usb, 0)
213 #include <config_distro_bootcmd.h>
214 #endif
215
216 #ifndef SPL_NO_MISC
217 /* Initial environment variables */
218 #define CONFIG_EXTRA_ENV_SETTINGS \
219 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
220 "ramdisk_addr=0x800000\0" \
221 "ramdisk_size=0x2000000\0" \
222 "fdt_high=0xffffffffffffffff\0" \
223 "initrd_high=0xffffffffffffffff\0" \
224 "fdt_addr=0x64f00000\0" \
225 "kernel_addr=0x65000000\0" \
226 "scriptaddr=0x80000000\0" \
227 "scripthdraddr=0x80080000\0" \
228 "fdtheader_addr_r=0x80100000\0" \
229 "kernelheader_addr_r=0x80200000\0" \
230 "load_addr=0xa0000000\0" \
231 "kernel_addr_r=0x81000000\0" \
232 "fdt_addr_r=0x90000000\0" \
233 "ramdisk_addr_r=0xa0000000\0" \
234 "kernel_start=0x1000000\0" \
235 "kernelheader_start=0x800000\0" \
236 "kernel_load=0xa0000000\0" \
237 "kernel_size=0x2800000\0" \
238 "kernelheader_size=0x40000\0" \
239 "kernel_addr_sd=0x8000\0" \
240 "kernel_size_sd=0x14000\0" \
241 "kernelhdr_addr_sd=0x4000\0" \
242 "kernelhdr_size_sd=0x10\0" \
243 "console=ttyS0,115200\0" \
244 CONFIG_MTDPARTS_DEFAULT "\0" \
245 BOOTENV \
246 "boot_scripts=ls1046ardb_boot.scr\0" \
247 "boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
248 "scan_dev_for_boot_part=" \
249 "part list ${devtype} ${devnum} devplist; " \
250 "env exists devplist || setenv devplist 1; " \
251 "for distro_bootpart in ${devplist}; do " \
252 "if fstype ${devtype} " \
253 "${devnum}:${distro_bootpart} " \
254 "bootfstype; then " \
255 "run scan_dev_for_boot; " \
256 "fi; " \
257 "done\0" \
258 "scan_dev_for_boot=" \
259 "echo Scanning ${devtype} " \
260 "${devnum}:${distro_bootpart}...; " \
261 "for prefix in ${boot_prefixes}; do " \
262 "run scan_dev_for_scripts; " \
263 "done;" \
264 "\0" \
265 "boot_a_script=" \
266 "load ${devtype} ${devnum}:${distro_bootpart} " \
267 "${scriptaddr} ${prefix}${script}; " \
268 "env exists secureboot && load ${devtype} " \
269 "${devnum}:${distro_bootpart} " \
270 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
271 "&& esbc_validate ${scripthdraddr};" \
272 "source ${scriptaddr}\0" \
273 "qspi_bootcmd=echo Trying load from qspi..;" \
274 "sf probe && sf read $load_addr " \
275 "$kernel_start $kernel_size; env exists secureboot " \
276 "&& sf read $kernelheader_addr_r $kernelheader_start " \
277 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
278 "bootm $load_addr#$board\0" \
279 "sd_bootcmd=echo Trying load from SD ..;" \
280 "mmcinfo; mmc read $load_addr " \
281 "$kernel_addr_sd $kernel_size_sd && " \
282 "env exists secureboot && mmc read $kernelheader_addr_r " \
283 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
284 " && esbc_validate ${kernelheader_addr_r};" \
285 "bootm $load_addr#$board\0"
286
287 #endif
288
289 /* Monitor Command Prompt */
290 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
291 #define CONFIG_SYS_LONGHELP
292
293 #define CONFIG_AUTO_COMPLETE
294 #define CONFIG_SYS_MAXARGS 64 /* max command args */
295
296 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
297
298 #include <asm/arch/soc.h>
299
300 #endif /* __LS1046A_COMMON_H */