include/configs/ls1046ardb.h

   1 /*
   2  * Copyright 2016 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1046ARDB_H__
   8 #define __LS1046ARDB_H__
   9
  10 #include "ls1046a_common.h"
  11
  12 #if defined(CONFIG_FSL_LS_PPA)
  13 #define CONFIG_ARMV8_PSCI
  14 #define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
  15 #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE           (1UL * 1024 * 1024)
  16
  17 #define CONFIG_SYS_LS_PPA_FW_IN_XIP
  18 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
  19 #define CONFIG_SYS_LS_PPA_FW_ADDR       0x40500000
  20 #endif
  21 #endif
  22
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #ifdef CONFIG_SD_BOOT
  26 #define CONFIG_SYS_TEXT_BASE            0x82000000
  27 #else
  28 #define CONFIG_SYS_TEXT_BASE            0x40100000
  29 #endif
  30
  31 #define CONFIG_SYS_CLK_FREQ             100000000
  32 #define CONFIG_DDR_CLK_FREQ             100000000
  33
  34 #define CONFIG_LAYERSCAPE_NS_ACCESS
  35 #define CONFIG_MISC_INIT_R
  36
  37 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  38 /* Physical Memory Map */
  39 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  40 #define CONFIG_NR_DRAM_BANKS            2
  41
  42 #define CONFIG_DDR_SPD
  43 #define SPD_EEPROM_ADDRESS              0x51
  44 #define CONFIG_SYS_SPD_BUS_NUM          0
  45
  46 #define CONFIG_DDR_ECC
  47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  48 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  49 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  50 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  51
  52 #ifdef CONFIG_RAMBOOT_PBL
  53 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
  54 #endif
  55
  56 #ifdef CONFIG_SD_BOOT
  57 #ifdef CONFIG_EMMC_BOOT
  58 #define CONFIG_SYS_FSL_PBL_RCW \
  59         board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
  60 #else
  61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
  62 #endif
  63 #endif
  64
  65 /* No NOR flash */
  66 #define CONFIG_SYS_NO_FLASH
  67
  68 /* IFC */
  69 #define CONFIG_FSL_IFC
  70
  71 /*
  72  * NAND Flash Definitions
  73  */
  74 #define CONFIG_NAND_FSL_IFC
  75
  76 #define CONFIG_SYS_NAND_BASE            0x7e800000
  77 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
  78
  79 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  80 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  81                                 | CSPR_PORT_SIZE_8      \
  82                                 | CSPR_MSEL_NAND        \
  83                                 | CSPR_V)
  84 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  85 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  86                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  87                                 | CSOR_NAND_ECC_MODE_8  /* 8-bit ECC */ \
  88                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
  89                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  90                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  91                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
  92
  93 #define CONFIG_SYS_NAND_ONFI_DETECTION
  94
  95 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
  96                                         FTIM0_NAND_TWP(0x18)   | \
  97                                         FTIM0_NAND_TWCHT(0x7) | \
  98                                         FTIM0_NAND_TWH(0xa))
  99 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 100                                         FTIM1_NAND_TWBE(0x39)  | \
 101                                         FTIM1_NAND_TRR(0xe)   | \
 102                                         FTIM1_NAND_TRP(0x18))
 103 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 104                                         FTIM2_NAND_TREH(0xa) | \
 105                                         FTIM2_NAND_TWHRE(0x1e))
 106 #define CONFIG_SYS_NAND_FTIM3           0x0
 107
 108 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 109 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 110 #define CONFIG_MTD_NAND_VERIFY_WRITE
 111 #define CONFIG_CMD_NAND
 112
 113 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 114
 115 /*
 116  * CPLD
 117  */
 118 #define CONFIG_SYS_CPLD_BASE            0x7fb00000
 119 #define CPLD_BASE_PHYS                  CONFIG_SYS_CPLD_BASE
 120
 121 #define CONFIG_SYS_CPLD_CSPR_EXT        (0x0)
 122 #define CONFIG_SYS_CPLD_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 123                                         CSPR_PORT_SIZE_8 | \
 124                                         CSPR_MSEL_GPCM | \
 125                                         CSPR_V)
 126 #define CONFIG_SYS_CPLD_AMASK           IFC_AMASK(64 * 1024)
 127 #define CONFIG_SYS_CPLD_CSOR            CSOR_NOR_ADM_SHIFT(16)
 128
 129 /* CPLD Timing parameters for IFC GPCM */
 130 #define CONFIG_SYS_CPLD_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
 131                                         FTIM0_GPCM_TEADC(0x0e) | \
 132                                         FTIM0_GPCM_TEAHC(0x0e))
 133 #define CONFIG_SYS_CPLD_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 134                                         FTIM1_GPCM_TRAD(0x3f))
 135 #define CONFIG_SYS_CPLD_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 136                                         FTIM2_GPCM_TCH(0xf) | \
 137                                         FTIM2_GPCM_TWP(0x3E))
 138 #define CONFIG_SYS_CPLD_FTIM3           0x0
 139
 140 /* IFC Timing Params */
 141 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 142 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 143 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 144 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 145 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 146 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 147 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 148 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 149
 150 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_CPLD_CSPR_EXT
 151 #define CONFIG_SYS_CSPR2                CONFIG_SYS_CPLD_CSPR
 152 #define CONFIG_SYS_AMASK2               CONFIG_SYS_CPLD_AMASK
 153 #define CONFIG_SYS_CSOR2                CONFIG_SYS_CPLD_CSOR
 154 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_CPLD_FTIM0
 155 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_CPLD_FTIM1
 156 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_CPLD_FTIM2
 157 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_CPLD_FTIM3
 158
 159 /* EEPROM */
 160 #define CONFIG_ID_EEPROM
 161 #define CONFIG_SYS_I2C_EEPROM_NXID
 162 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 163 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 164 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 165 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 166 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 167 #define I2C_RETIMER_ADDR                        0x18
 168
 169 /*
 170  * Environment
 171  */
 172 #define CONFIG_ENV_OVERWRITE
 173
 174 #if defined(CONFIG_SD_BOOT)
 175 #define CONFIG_ENV_IS_IN_MMC
 176 #define CONFIG_SYS_MMC_ENV_DEV          0
 177 #define CONFIG_ENV_OFFSET               (1024 * 1024)
 178 #define CONFIG_ENV_SIZE                 0x2000
 179 #else
 180 #define CONFIG_ENV_IS_IN_SPI_FLASH
 181 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 182 #define CONFIG_ENV_OFFSET               0x200000        /* 2MB */
 183 #define CONFIG_ENV_SECT_SIZE            0x40000         /* 256KB */
 184 #endif
 185
 186 /* FMan */
 187 #ifdef CONFIG_SYS_DPAA_FMAN
 188 #define CONFIG_FMAN_ENET
 189 #define CONFIG_PHYLIB
 190 #define CONFIG_PHYLIB_10G
 191 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 192
 193 #define CONFIG_PHY_REALTEK
 194 #define CONFIG_PHY_AQUANTIA
 195 #define AQR105_IRQ_MASK                 0x80000000
 196
 197 #define RGMII_PHY1_ADDR                 0x1
 198 #define RGMII_PHY2_ADDR                 0x2
 199
 200 #define SGMII_PHY1_ADDR                 0x3
 201 #define SGMII_PHY2_ADDR                 0x4
 202
 203 #define FM1_10GEC1_PHY_ADDR             0x0
 204
 205 #define CONFIG_ETHPRIME                 "FM1@DTSEC3"
 206 #endif
 207
 208 /* QSPI device */
 209 #ifdef CONFIG_FSL_QSPI
 210 #define CONFIG_SPI_FLASH_SPANSION
 211 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
 212 #define FSL_QSPI_FLASH_NUM              2
 213 #define CONFIG_SPI_FLASH_BAR
 214 #endif
 215
 216 /* SATA */
 217 #define CONFIG_LIBATA
 218 #define CONFIG_SCSI_AHCI
 219 #define CONFIG_SCSI_AHCI_PLAT
 220 #define CONFIG_SCSI
 221 #define CONFIG_DOS_PARTITION
 222 #define CONFIG_BOARD_LATE_INIT
 223
 224 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
 225
 226 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
 227 #define CONFIG_SYS_SCSI_MAX_LUN                 1
 228 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 229                                                 CONFIG_SYS_SCSI_MAX_LUN)
 230 #define CONFIG_BOOTCOMMAND              "sf probe 0:0;sf read $kernel_load" \
 231                                         "$kernel_start $kernel_size;" \
 232                                         "bootm $kernel_load"
 233
 234 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \
 235                         "15m(u-boot),48m(kernel.itb);" \
 236                         "7e800000.flash:16m(nand_uboot)," \
 237                         "48m(nand_kernel),448m(nand_free)"
 238
 239 #endif /* __LS1046ARDB_H__ */