include/configs/ls1088a_common.h

   1 /*
   2  * Copyright 2017 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1088_COMMON_H
   8 #define __LS1088_COMMON_H
   9
  10 /* SPL build */
  11 #ifdef CONFIG_SPL_BUILD
  12 #define SPL_NO_BOARDINFO
  13 #define SPL_NO_QIXIS
  14 #define SPL_NO_PCI
  15 #define SPL_NO_ENV
  16 #define SPL_NO_RTC
  17 #define SPL_NO_USB
  18 #define SPL_NO_SATA
  19 #define SPL_NO_QSPI
  20 #define SPL_NO_IFC
  21 #undef CONFIG_DISPLAY_CPUINFO
  22 #endif
  23
  24 #define CONFIG_REMAKE_ELF
  25 #define CONFIG_FSL_LAYERSCAPE
  26 #define CONFIG_MP
  27
  28 #include <asm/arch/stream_id_lsch3.h>
  29 #include <asm/arch/config.h>
  30 #include <asm/arch/soc.h>
  31
  32 /* Link Definitions */
  33 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  34
  35 /* Link Definitions */
  36
  37 #define CONFIG_SUPPORT_RAW_INITRD
  38
  39 #ifdef CONFIG_QSPI_BOOT
  40 #define CONFIG_SYS_FSL_QSPI_BASE        0x20000000
  41 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
  42 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FSL_QSPI_BASE + \
  43                                                 CONFIG_ENV_OFFSET)
  44 #endif
  45
  46 #define CONFIG_SKIP_LOWLEVEL_INIT
  47
  48 #if !defined(CONFIG_SD_BOOT)
  49 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  50 #endif
  51
  52 #define CONFIG_VERY_BIG_RAM
  53 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  54 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  55 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  56 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  57 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       1
  58 /*
  59  * SMP Definitinos
  60  */
  61 #define CPU_RELEASE_ADDR                secondary_boot_func
  62
  63 #ifdef CONFIG_PCI
  64 #define CONFIG_CMD_PCI
  65 #endif
  66
  67 /* Size of malloc() pool */
  68 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 2048 * 1024)
  69
  70 /* I2C */
  71 #define CONFIG_SYS_I2C
  72 #define CONFIG_SYS_I2C_MXC
  73 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
  74 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
  75 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
  76 #define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
  77
  78 /* Serial Port */
  79 #define CONFIG_CONS_INDEX       1
  80 #define CONFIG_SYS_NS16550_SERIAL
  81 #define CONFIG_SYS_NS16550_REG_SIZE     1
  82 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
  83
  84 #define CONFIG_BAUDRATE                 115200
  85 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  86
  87 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
  88 /* IFC */
  89 #define CONFIG_FSL_IFC
  90 #endif
  91
  92 /*
  93  * During booting, IFC is mapped at the region of 0x30000000.
  94  * But this region is limited to 256MB. To accommodate NOR, promjet
  95  * and FPGA. This region is divided as below:
  96  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
  97  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
  98  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
  99  *
 100  * To accommodate bigger NOR flash and other devices, we will map IFC
 101  * chip selects to as below:
 102  * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
 103  * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
 104  * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
 105  * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
 106  * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
 107  *
 108  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 109  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 110  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 111  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 112  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 113  */
 114
 115 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
 116 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
 117 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 118
 119 #define CONFIG_SYS_FLASH1_BASE_PHYS             0xC0000000
 120 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY       0x8000000
 121
 122 #ifndef __ASSEMBLY__
 123 unsigned long long get_qixis_addr(void);
 124 #endif
 125
 126 #define QIXIS_BASE                              get_qixis_addr()
 127 #define QIXIS_BASE_PHYS                         0x20000000
 128 #define QIXIS_BASE_PHYS_EARLY                   0xC000000
 129
 130
 131 #define CONFIG_SYS_NAND_BASE                    0x530000000ULL
 132 #define CONFIG_SYS_NAND_BASE_PHYS               0x30000000
 133
 134
 135 /* MC firmware */
 136 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 137 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH     0x20000
 138 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 139 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH     0x20000
 140 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 141 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH    0x200000
 142 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET   0x07000000
 143
 144 /* Define phy_reset function to boot the MC based on mcinitcmd.
 145  * This happens late enough to properly fixup u-boot env MAC addresses.
 146  */
 147 #define CONFIG_RESET_PHY_R
 148
 149 /*
 150  * Carve out a DDR region which will not be used by u-boot/Linux
 151  *
 152  * It will be used by MC and Debug Server. The MC region must be
 153  * 512MB aligned, so the min size to hide is 512MB.
 154  */
 155
 156 #if defined(CONFIG_FSL_MC_ENET)
 157 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE            (512UL * 1024 * 1024)
 158 #endif
 159 /* Command line configuration */
 160 #define CONFIG_CMD_GREPENV
 161 #define CONFIG_CMD_CACHE
 162
 163 /* Miscellaneous configurable options */
 164 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 165
 166 /* SATA */
 167 #ifdef CONFIG_SCSI
 168 #define CONFIG_SCSI_AHCI_PLAT
 169 #define CONFIG_SYS_SATA1                AHCI_BASE_ADDR1
 170
 171 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
 172 #define CONFIG_SYS_SCSI_MAX_LUN         1
 173 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 174                                         CONFIG_SYS_SCSI_MAX_LUN)
 175 #endif
 176
 177 /* Physical Memory Map */
 178 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 179
 180 #define CONFIG_NR_DRAM_BANKS            2
 181
 182 #define CONFIG_HWCONFIG
 183 #define HWCONFIG_BUFFER_SIZE            128
 184
 185 /* #define CONFIG_DISPLAY_CPUINFO */
 186
 187 #ifndef SPL_NO_ENV
 188 /* Allow to overwrite serial and ethaddr */
 189 #define CONFIG_ENV_OVERWRITE
 190
 191 /* Initial environment variables */
 192 #define CONFIG_EXTRA_ENV_SETTINGS               \
 193         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 194         "loadaddr=0x80100000\0"                 \
 195         "kernel_addr=0x100000\0"                \
 196         "ramdisk_addr=0x800000\0"               \
 197         "ramdisk_size=0x2000000\0"              \
 198         "fdt_high=0xa0000000\0"                 \
 199         "initrd_high=0xffffffffffffffff\0"      \
 200         "kernel_start=0x581000000\0"            \
 201         "kernel_load=0xa0000000\0"              \
 202         "kernel_size=0x2800000\0"               \
 203         "console=ttyAMA0,38400n8\0"             \
 204         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 205         " 0x580e00000 \0"
 206
 207 #define CONFIG_BOOTARGS         "console=ttyS0,115200 root=/dev/ram0 " \
 208                                 "earlycon=uart8250,mmio,0x21c0500 " \
 209                                 "ramdisk_size=0x3000000 default_hugepagesz=2m" \
 210                                 " hugepagesz=2m hugepages=256"
 211 #if defined(CONFIG_QSPI_BOOT)
 212 #define CONFIG_BOOTCOMMAND      "sf probe 0:0;" \
 213                                 "sf read 0x80200000 0xd00000 0x100000;"\
 214                                 " fsl_mc apply dpl 0x80200000 &&" \
 215                                 " sf read $kernel_load $kernel_start" \
 216                                 " $kernel_size && bootm $kernel_load"
 217 #elif defined(CONFIG_SD_BOOT)
 218 #define CONFIG_BOOTCOMMAND      "mmcinfo;mmc read 0x80200000 0x6800 0x800;"\
 219                                 " fsl_mc apply dpl 0x80200000 &&" \
 220                                 " mmc read $kernel_load $kernel_start" \
 221                                 " $kernel_size && bootm $kernel_load"
 222 #else /* NOR BOOT*/
 223 #define CONFIG_BOOTCOMMAND      "fsl_mc apply dpl 0x580d00000 &&" \
 224                                 " cp.b $kernel_start $kernel_load" \
 225                                 " $kernel_size && bootm $kernel_load"
 226 #endif
 227 #endif
 228
 229 /* Monitor Command Prompt */
 230 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 231 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 232                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 233 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 234 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 235 #define CONFIG_SYS_LONGHELP
 236 #ifndef SPL_NO_ENV
 237 #define CONFIG_CMDLINE_EDITING          1
 238 #endif
 239 #define CONFIG_AUTO_COMPLETE
 240 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 241
 242 #ifdef CONFIG_SPL
 243 #define CONFIG_SPL_BSS_START_ADDR      0x80100000
 244 #define CONFIG_SPL_BSS_MAX_SIZE                0x00100000
 245 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
 246 #define CONFIG_SPL_MAX_SIZE            0x16000
 247 #define CONFIG_SPL_STACK               (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
 248 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
 249 #define CONFIG_SPL_TEXT_BASE           0x1800a000
 250
 251 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
 252 #define CONFIG_SYS_SPL_MALLOC_START    0x80200000
 253
 254 #ifdef CONFIG_SECURE_BOOT
 255 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
 256 /*
 257  * HDR would be appended at end of image and copied to DDR along
 258  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 259  * size increases then increase this size in case of secure boot as
 260  * it uses raw u-boot image instead of fit image.
 261  */
 262 #define CONFIG_SYS_MONITOR_LEN         (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 263 #else
 264 #define CONFIG_SYS_MONITOR_LEN         0x100000
 265 #endif /* ifdef CONFIG_SECURE_BOOT */
 266
 267 #endif
 268 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 269
 270 #endif /* __LS1088_COMMON_H */