include/configs/ls1088a_common.h

   1 /*
   2  * Copyright 2017 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1088_COMMON_H
   8 #define __LS1088_COMMON_H
   9
  10 /* SPL build */
  11 #ifdef CONFIG_SPL_BUILD
  12 #define SPL_NO_BOARDINFO
  13 #define SPL_NO_QIXIS
  14 #define SPL_NO_PCI
  15 #define SPL_NO_ENV
  16 #define SPL_NO_RTC
  17 #define SPL_NO_USB
  18 #define SPL_NO_SATA
  19 #define SPL_NO_QSPI
  20 #define SPL_NO_IFC
  21 #undef CONFIG_DISPLAY_CPUINFO
  22 #endif
  23
  24 #define CONFIG_REMAKE_ELF
  25 #define CONFIG_FSL_LAYERSCAPE
  26 #define CONFIG_MP
  27
  28 #include <asm/arch/stream_id_lsch3.h>
  29 #include <asm/arch/config.h>
  30 #include <asm/arch/soc.h>
  31
  32 /* Link Definitions */
  33 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  34
  35 /* Link Definitions */
  36 #ifdef CONFIG_SPL
  37 #define CONFIG_SYS_TEXT_BASE            0x80400000
  38 #else
  39 #ifdef CONFIG_QSPI_BOOT
  40 #define CONFIG_SYS_TEXT_BASE            0x20100000
  41 #else
  42 #define CONFIG_SYS_TEXT_BASE            0x30100000
  43 #endif
  44 #endif
  45
  46 #define CONFIG_SUPPORT_RAW_INITRD
  47
  48 #ifdef CONFIG_QSPI_BOOT
  49 #define CONFIG_SYS_FSL_QSPI_BASE        0x20000000
  50 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
  51 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FSL_QSPI_BASE + \
  52                                                 CONFIG_ENV_OFFSET)
  53 #endif
  54
  55 #define CONFIG_SKIP_LOWLEVEL_INIT
  56
  57 #if !defined(CONFIG_SD_BOOT)
  58 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  59 #endif
  60
  61 #define CONFIG_VERY_BIG_RAM
  62 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  63 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  64 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  65 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  66 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       1
  67 /*
  68  * SMP Definitinos
  69  */
  70 #define CPU_RELEASE_ADDR                secondary_boot_func
  71
  72 #ifdef CONFIG_PCI
  73 #define CONFIG_CMD_PCI
  74 #endif
  75
  76 /* Size of malloc() pool */
  77 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 2048 * 1024)
  78
  79 /* I2C */
  80 #define CONFIG_SYS_I2C
  81 #define CONFIG_SYS_I2C_MXC
  82 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
  83 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
  84 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
  85 #define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
  86
  87 /* Serial Port */
  88 #define CONFIG_CONS_INDEX       1
  89 #define CONFIG_SYS_NS16550_SERIAL
  90 #define CONFIG_SYS_NS16550_REG_SIZE     1
  91 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
  92
  93 #define CONFIG_BAUDRATE                 115200
  94 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  95
  96 #if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
  97 /* IFC */
  98 #define CONFIG_FSL_IFC
  99 #endif
 100
 101 /*
 102  * During booting, IFC is mapped at the region of 0x30000000.
 103  * But this region is limited to 256MB. To accommodate NOR, promjet
 104  * and FPGA. This region is divided as below:
 105  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 106  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 107  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 108  *
 109  * To accommodate bigger NOR flash and other devices, we will map IFC
 110  * chip selects to as below:
 111  * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
 112  * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
 113  * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
 114  * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
 115  * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
 116  *
 117  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 118  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 119  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 120  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 121  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 122  */
 123
 124 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
 125 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
 126 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 127
 128 #define CONFIG_SYS_FLASH1_BASE_PHYS             0xC0000000
 129 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY       0x8000000
 130
 131 #ifndef __ASSEMBLY__
 132 unsigned long long get_qixis_addr(void);
 133 #endif
 134
 135 #define QIXIS_BASE                              get_qixis_addr()
 136 #define QIXIS_BASE_PHYS                         0x20000000
 137 #define QIXIS_BASE_PHYS_EARLY                   0xC000000
 138
 139
 140 #define CONFIG_SYS_NAND_BASE                    0x530000000ULL
 141 #define CONFIG_SYS_NAND_BASE_PHYS               0x30000000
 142
 143
 144 /* MC firmware */
 145 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 146 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH     0x20000
 147 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 148 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH     0x20000
 149 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 150 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH    0x200000
 151 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET   0x07000000
 152
 153 /* Define phy_reset function to boot the MC based on mcinitcmd.
 154  * This happens late enough to properly fixup u-boot env MAC addresses.
 155  */
 156 #define CONFIG_RESET_PHY_R
 157
 158 /*
 159  * Carve out a DDR region which will not be used by u-boot/Linux
 160  *
 161  * It will be used by MC and Debug Server. The MC region must be
 162  * 512MB aligned, so the min size to hide is 512MB.
 163  */
 164
 165 #if defined(CONFIG_FSL_MC_ENET)
 166 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE            (512UL * 1024 * 1024)
 167 #endif
 168 /* Command line configuration */
 169 #define CONFIG_CMD_GREPENV
 170 #define CONFIG_CMD_CACHE
 171
 172 /* Miscellaneous configurable options */
 173 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 174
 175 /* SATA */
 176 #ifdef CONFIG_SCSI
 177 #define CONFIG_SCSI_AHCI_PLAT
 178 #define CONFIG_SYS_SATA1                AHCI_BASE_ADDR1
 179
 180 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     1
 181 #define CONFIG_SYS_SCSI_MAX_LUN         1
 182 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 183                                         CONFIG_SYS_SCSI_MAX_LUN)
 184 #endif
 185
 186 /* Physical Memory Map */
 187 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 188
 189 #define CONFIG_NR_DRAM_BANKS            2
 190
 191 #define CONFIG_HWCONFIG
 192 #define HWCONFIG_BUFFER_SIZE            128
 193
 194 /* #define CONFIG_DISPLAY_CPUINFO */
 195
 196 #ifndef SPL_NO_ENV
 197 /* Allow to overwrite serial and ethaddr */
 198 #define CONFIG_ENV_OVERWRITE
 199
 200 /* Initial environment variables */
 201 #define CONFIG_EXTRA_ENV_SETTINGS               \
 202         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 203         "loadaddr=0x80100000\0"                 \
 204         "kernel_addr=0x100000\0"                \
 205         "ramdisk_addr=0x800000\0"               \
 206         "ramdisk_size=0x2000000\0"              \
 207         "fdt_high=0xa0000000\0"                 \
 208         "initrd_high=0xffffffffffffffff\0"      \
 209         "kernel_start=0x581000000\0"            \
 210         "kernel_load=0xa0000000\0"              \
 211         "kernel_size=0x2800000\0"               \
 212         "console=ttyAMA0,38400n8\0"             \
 213         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 214         " 0x580e00000 \0"
 215
 216 #define CONFIG_BOOTARGS         "console=ttyS0,115200 root=/dev/ram0 " \
 217                                 "earlycon=uart8250,mmio,0x21c0500 " \
 218                                 "ramdisk_size=0x3000000 default_hugepagesz=2m" \
 219                                 " hugepagesz=2m hugepages=256"
 220 #if defined(CONFIG_QSPI_BOOT)
 221 #define CONFIG_BOOTCOMMAND      "sf probe 0:0;" \
 222                                 "sf read 0x80200000 0xd00000 0x100000;"\
 223                                 " fsl_mc apply dpl 0x80200000 &&" \
 224                                 " sf read $kernel_load $kernel_start" \
 225                                 " $kernel_size && bootm $kernel_load"
 226 #elif defined(CONFIG_SD_BOOT)
 227 #define CONFIG_BOOTCOMMAND      "mmcinfo;mmc read 0x80200000 0x6800 0x800;"\
 228                                 " fsl_mc apply dpl 0x80200000 &&" \
 229                                 " mmc read $kernel_load $kernel_start" \
 230                                 " $kernel_size && bootm $kernel_load"
 231 #else /* NOR BOOT*/
 232 #define CONFIG_BOOTCOMMAND      "fsl_mc apply dpl 0x580d00000 &&" \
 233                                 " cp.b $kernel_start $kernel_load" \
 234                                 " $kernel_size && bootm $kernel_load"
 235 #endif
 236 #endif
 237
 238 /* Monitor Command Prompt */
 239 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 240 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 241                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 242 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 243 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 244 #define CONFIG_SYS_LONGHELP
 245 #ifndef SPL_NO_ENV
 246 #define CONFIG_CMDLINE_EDITING          1
 247 #endif
 248 #define CONFIG_AUTO_COMPLETE
 249 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 250
 251 #ifdef CONFIG_SPL
 252 #define CONFIG_SPL_BSS_START_ADDR      0x80100000
 253 #define CONFIG_SPL_BSS_MAX_SIZE                0x00100000
 254 #define CONFIG_SPL_FRAMEWORK
 255 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
 256 #define CONFIG_SPL_MAX_SIZE            0x16000
 257 #define CONFIG_SPL_STACK               (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
 258 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
 259 #define CONFIG_SPL_TEXT_BASE           0x1800a000
 260
 261 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
 262 #define CONFIG_SYS_SPL_MALLOC_START    0x80200000
 263
 264 #ifdef CONFIG_SECURE_BOOT
 265 #define CONFIG_U_BOOT_HDR_SIZE          (16 << 10)
 266 /*
 267  * HDR would be appended at end of image and copied to DDR along
 268  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 269  * size increases then increase this size in case of secure boot as
 270  * it uses raw u-boot image instead of fit image.
 271  */
 272 #define CONFIG_SYS_MONITOR_LEN         (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 273 #else
 274 #define CONFIG_SYS_MONITOR_LEN         0x100000
 275 #endif /* ifdef CONFIG_SECURE_BOOT */
 276
 277 #endif
 278 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 279
 280 #endif /* __LS1088_COMMON_H */