include/configs/ls2080a_common.h

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_COMMON_H
   8 #define __LS2_COMMON_H
   9
  10 #define CONFIG_REMAKE_ELF
  11 #define CONFIG_FSL_LAYERSCAPE
  12 #define CONFIG_FSL_LSCH3
  13 #define CONFIG_MP
  14 #define CONFIG_GICV3
  15 #define CONFIG_FSL_TZPC_BP147
  16
  17 #include <asm/arch/ls2080a_stream_id.h>
  18 #include <asm/arch/config.h>
  19 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
  20 #define CONFIG_SYS_HAS_SERDES
  21 #endif
  22
  23 /* Link Definitions */
  24 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  25
  26 /* We need architecture specific misc initializations */
  27 #define CONFIG_ARCH_MISC_INIT
  28
  29 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  30
  31 /* Link Definitions */
  32 #ifndef CONFIG_QSPI_BOOT
  33 #ifdef CONFIG_SPL
  34 #define CONFIG_SYS_TEXT_BASE            0x80400000
  35 #else
  36 #define CONFIG_SYS_TEXT_BASE            0x30100000
  37 #endif
  38 #endif
  39
  40 #ifdef CONFIG_EMU
  41 #define CONFIG_SYS_NO_FLASH
  42 #endif
  43
  44 #define CONFIG_SUPPORT_RAW_INITRD
  45
  46 #define CONFIG_SKIP_LOWLEVEL_INIT
  47 #define CONFIG_BOARD_EARLY_INIT_F       1
  48
  49 #ifndef CONFIG_SPL
  50 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  51 #endif
  52 #ifndef CONFIG_SYS_FSL_DDR4
  53 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  54 #define CONFIG_SYS_DDR_RAW_TIMING
  55 #endif
  56
  57 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  58
  59 #define CONFIG_VERY_BIG_RAM
  60 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  61 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  63 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  64 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       2
  65
  66 /*
  67  * SMP Definitinos
  68  */
  69 #define CPU_RELEASE_ADDR                secondary_boot_func
  70
  71 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
  72 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  73 #define CONFIG_SYS_DP_DDR_BASE          0x6000000000ULL
  74 /*
  75  * DDR controller use 0 as the base address for binding.
  76  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  77  */
  78 #define CONFIG_SYS_DP_DDR_BASE_PHY      0
  79 #define CONFIG_DP_DDR_CTRL              2
  80 #define CONFIG_DP_DDR_NUM_CTRLS         1
  81 #endif
  82
  83 /* Generic Timer Definitions */
  84 /*
  85  * This is not an accurate number. It is used in start.S. The frequency
  86  * will be udpated later when get_bus_freq(0) is available.
  87  */
  88 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  89
  90 /* Size of malloc() pool */
  91 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 2048 * 1024)
  92
  93 /* I2C */
  94 #define CONFIG_SYS_I2C
  95 #define CONFIG_SYS_I2C_MXC
  96 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
  97 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
  98 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
  99 #define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
 100
 101 /* Serial Port */
 102 #define CONFIG_CONS_INDEX       1
 103 #define CONFIG_SYS_NS16550_SERIAL
 104 #define CONFIG_SYS_NS16550_REG_SIZE     1
 105 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 106
 107 #define CONFIG_BAUDRATE                 115200
 108 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 109
 110 /* IFC */
 111 #define CONFIG_FSL_IFC
 112
 113 /*
 114  * During booting, IFC is mapped at the region of 0x30000000.
 115  * But this region is limited to 256MB. To accommodate NOR, promjet
 116  * and FPGA. This region is divided as below:
 117  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 118  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 119  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 120  *
 121  * To accommodate bigger NOR flash and other devices, we will map IFC
 122  * chip selects to as below:
 123  * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
 124  * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
 125  * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
 126  * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
 127  * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
 128  *
 129  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 130  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 131  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 132  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 133  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 134  */
 135
 136 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
 137 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
 138 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 139
 140 #define CONFIG_SYS_FLASH1_BASE_PHYS             0xC0000000
 141 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY       0x8000000
 142
 143 #ifndef __ASSEMBLY__
 144 unsigned long long get_qixis_addr(void);
 145 #endif
 146 #define QIXIS_BASE                              get_qixis_addr()
 147 #define QIXIS_BASE_PHYS                         0x20000000
 148 #define QIXIS_BASE_PHYS_EARLY                   0xC000000
 149 #define QIXIS_STAT_PRES1                        0xb
 150 #define QIXIS_SDID_MASK                         0x07
 151 #define QIXIS_ESDHC_NO_ADAPTER                  0x7
 152
 153 #define CONFIG_SYS_NAND_BASE                    0x530000000ULL
 154 #define CONFIG_SYS_NAND_BASE_PHYS               0x30000000
 155
 156 /* Debug Server firmware */
 157 #define CONFIG_FSL_DEBUG_SERVER
 158 /* 2 sec timeout */
 159 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT                 (2 * 1000 * 1000)
 160
 161 /* MC firmware */
 162 #define CONFIG_FSL_MC_ENET
 163 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 164 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH     0x20000
 165 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 166 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH     0x20000
 167 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 168 /* For LS2085A */
 169 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH    0x200000
 170 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET   0x07000000
 171
 172 /*
 173  * Carve out a DDR region which will not be used by u-boot/Linux
 174  *
 175  * It will be used by MC and Debug Server. The MC region must be
 176  * 512MB aligned, so the min size to hide is 512MB.
 177  */
 178 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
 179 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE     (254UL * 1024 * 1024)
 180 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE            (512UL * 1024 * 1024)
 181 #define CONFIG_SYS_MC_RSV_MEM_ALIGN                     (512UL * 1024 * 1024)
 182 #endif
 183
 184 /* PCIe */
 185 #define CONFIG_PCIE1            /* PCIE controller 1 */
 186 #define CONFIG_PCIE2            /* PCIE controller 2 */
 187 #define CONFIG_PCIE3            /* PCIE controller 3 */
 188 #define CONFIG_PCIE4            /* PCIE controller 4 */
 189 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 190 #ifdef CONFIG_LS2080A
 191 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
 192 #endif
 193
 194 #define CONFIG_SYS_PCI_64BIT
 195
 196 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 197 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 198 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 199 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 200
 201 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 202 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 203 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 204
 205 #define CONFIG_SYS_PCIE_MEM_BUS         0x40000000
 206 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x40000000
 207 #define CONFIG_SYS_PCIE_MEM_SIZE        0x40000000      /* 1G */
 208
 209 /* Command line configuration */
 210 #define CONFIG_CMD_ENV
 211
 212 /* Miscellaneous configurable options */
 213 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 214 #define CONFIG_ARCH_EARLY_INIT_R
 215
 216 /* Physical Memory Map */
 217 /* fixme: these need to be checked against the board */
 218 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 219
 220 #define CONFIG_NR_DRAM_BANKS            3
 221
 222 #define CONFIG_HWCONFIG
 223 #define HWCONFIG_BUFFER_SIZE            128
 224
 225 #define CONFIG_DISPLAY_CPUINFO
 226
 227 /* Allow to overwrite serial and ethaddr */
 228 #define CONFIG_ENV_OVERWRITE
 229
 230 /* Initial environment variables */
 231 #define CONFIG_EXTRA_ENV_SETTINGS               \
 232         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 233         "loadaddr=0x80100000\0"                 \
 234         "kernel_addr=0x100000\0"                \
 235         "ramdisk_addr=0x800000\0"               \
 236         "ramdisk_size=0x2000000\0"              \
 237         "fdt_high=0xa0000000\0"                 \
 238         "initrd_high=0xffffffffffffffff\0"      \
 239         "kernel_start=0x581200000\0"            \
 240         "kernel_load=0xa0000000\0"              \
 241         "kernel_size=0x2800000\0"               \
 242         "console=ttyAMA0,38400n8\0"             \
 243         "mcinitcmd=fsl_mc start mc 0x580300000" \
 244         " 0x580800000 \0"
 245
 246 #define CONFIG_BOOTARGS         "console=ttyS0,115200 root=/dev/ram0 " \
 247                                 "earlycon=uart8250,mmio,0x21c0500 " \
 248                                 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
 249                                 " hugepagesz=2m hugepages=256"
 250 #define CONFIG_BOOTCOMMAND      "fsl_mc apply dpl 0x580700000 &&" \
 251                                 " cp.b $kernel_start $kernel_load" \
 252                                 " $kernel_size && bootm $kernel_load"
 253
 254 /* Monitor Command Prompt */
 255 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 256 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 257                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 258 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 259 #define CONFIG_SYS_LONGHELP
 260 #define CONFIG_CMDLINE_EDITING          1
 261 #define CONFIG_AUTO_COMPLETE
 262 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 263
 264 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 265
 266 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 267 #define CONFIG_SPL_BSS_MAX_SIZE         0x00100000
 268 #define CONFIG_SPL_FRAMEWORK
 269 #define CONFIG_SPL_I2C_SUPPORT
 270 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
 271 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 272 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 273 #define CONFIG_SPL_MAX_SIZE             0x16000
 274 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 275 #define CONFIG_SPL_NAND_SUPPORT
 276 #define CONFIG_SPL_SERIAL_SUPPORT
 277 #define CONFIG_SPL_STACK                (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
 278 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 279 #define CONFIG_SPL_TEXT_BASE            0x1800a000
 280
 281 #define CONFIG_SYS_NAND_U_BOOT_DST      0x80400000
 282 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 283 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x00100000
 284 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 285 #define CONFIG_SYS_MONITOR_LEN          (640 * 1024)
 286
 287 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 288
 289 /* Hash command with SHA acceleration supported in hardware */
 290 #ifdef CONFIG_FSL_CAAM
 291 #define CONFIG_CMD_HASH
 292 #define CONFIG_SHA_HW_ACCEL
 293 #endif
 294
 295 #endif /* __LS2_COMMON_H */