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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/ls2080aqds.h
3 * Copyright 2015 Freescale Semiconductor
5 * SPDX-License-Identifier: GPL-2.0+
11 #include "ls2080a_common.h"
14 unsigned long get_board_sys_clk(void);
15 unsigned long get_board_ddr_clk(void);
18 #ifdef CONFIG_FSL_QSPI
19 #undef CONFIG_CMD_IMLS
20 #define CONFIG_QIXIS_I2C_ACCESS
21 #define CONFIG_SYS_I2C_EARLY_INIT
22 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
25 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
26 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
27 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
28 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
30 #define CONFIG_DDR_SPD
31 #define CONFIG_DDR_ECC
32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
34 #define SPD_EEPROM_ADDRESS1 0x51
35 #define SPD_EEPROM_ADDRESS2 0x52
36 #define SPD_EEPROM_ADDRESS3 0x53
37 #define SPD_EEPROM_ADDRESS4 0x54
38 #define SPD_EEPROM_ADDRESS5 0x55
39 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
47 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
51 #define CONFIG_SCSI_AHCI
52 #define CONFIG_SCSI_AHCI_PLAT
55 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
56 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
58 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
59 #define CONFIG_SYS_SCSI_MAX_LUN 1
60 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
61 CONFIG_SYS_SCSI_MAX_LUN)
63 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
65 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
66 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
67 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
69 #define CONFIG_SYS_NOR0_CSPR \
70 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
74 #define CONFIG_SYS_NOR0_CSPR_EARLY \
75 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
79 #define CONFIG_SYS_NOR1_CSPR \
80 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
84 #define CONFIG_SYS_NOR1_CSPR_EARLY \
85 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
89 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
90 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
91 FTIM0_NOR_TEADC(0x5) | \
93 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
94 FTIM1_NOR_TRAD_NOR(0x1a) |\
95 FTIM1_NOR_TSEQRAD_NOR(0x13))
96 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
97 FTIM2_NOR_TCH(0x4) | \
98 FTIM2_NOR_TWPH(0x0E) | \
100 #define CONFIG_SYS_NOR_FTIM3 0x04000000
101 #define CONFIG_SYS_IFC_CCR 0x01000000
103 #ifdef CONFIG_MTD_NOR_FLASH
104 #define CONFIG_FLASH_CFI_DRIVER
105 #define CONFIG_SYS_FLASH_CFI
106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
107 #define CONFIG_SYS_FLASH_QUIET_TEST
108 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
110 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
111 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
115 #define CONFIG_SYS_FLASH_EMPTY_INFO
116 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
117 CONFIG_SYS_FLASH_BASE + 0x40000000}
120 #define CONFIG_NAND_FSL_IFC
121 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
122 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
124 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
125 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
126 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
127 | CSPR_MSEL_NAND /* MSEL = NAND */ \
129 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
131 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
132 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
133 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
134 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
135 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
136 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
137 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
139 #define CONFIG_SYS_NAND_ONFI_DETECTION
141 /* ONFI NAND Flash mode0 Timing Params */
142 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
143 FTIM0_NAND_TWP(0x18) | \
144 FTIM0_NAND_TWCHT(0x07) | \
145 FTIM0_NAND_TWH(0x0a))
146 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
147 FTIM1_NAND_TWBE(0x39) | \
148 FTIM1_NAND_TRR(0x0e) | \
149 FTIM1_NAND_TRP(0x18))
150 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
151 FTIM2_NAND_TREH(0x0a) | \
152 FTIM2_NAND_TWHRE(0x1e))
153 #define CONFIG_SYS_NAND_FTIM3 0x0
155 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
156 #define CONFIG_SYS_MAX_NAND_DEVICE 1
157 #define CONFIG_MTD_NAND_VERIFY_WRITE
158 #define CONFIG_CMD_NAND
160 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
162 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
163 #define QIXIS_LBMAP_SWITCH 0x06
164 #define QIXIS_LBMAP_MASK 0x0f
165 #define QIXIS_LBMAP_SHIFT 0
166 #define QIXIS_LBMAP_DFLTBANK 0x00
167 #define QIXIS_LBMAP_ALTBANK 0x04
168 #define QIXIS_LBMAP_NAND 0x09
169 #define QIXIS_LBMAP_QSPI 0x0f
170 #define QIXIS_RST_CTL_RESET 0x31
171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
172 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
174 #define QIXIS_RCW_SRC_NAND 0x107
175 #define QIXIS_RCW_SRC_QSPI 0x62
176 #define QIXIS_RST_FORCE_MEM 0x01
178 #define CONFIG_SYS_CSPR3_EXT (0x0)
179 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
183 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
188 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
189 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
190 /* QIXIS Timing parameters for IFC CS3 */
191 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
192 FTIM0_GPCM_TEADC(0x0e) | \
193 FTIM0_GPCM_TEAHC(0x0e))
194 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
195 FTIM1_GPCM_TRAD(0x3f))
196 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
197 FTIM2_GPCM_TCH(0xf) | \
198 FTIM2_GPCM_TWP(0x3E))
199 #define CONFIG_SYS_CS3_FTIM3 0x0
201 #if defined(CONFIG_SPL)
202 #if defined(CONFIG_NAND_BOOT)
203 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
204 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
205 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
206 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
207 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
208 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
209 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
210 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
211 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
212 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
213 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
214 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
215 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
216 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
217 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
218 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
219 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
220 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
221 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
222 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
223 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
224 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
225 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
226 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
227 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
228 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
229 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
231 #define CONFIG_ENV_IS_IN_NAND
232 #define CONFIG_ENV_OFFSET (896 * 1024)
233 #define CONFIG_ENV_SECT_SIZE 0x20000
234 #define CONFIG_ENV_SIZE 0x2000
235 #define CONFIG_SPL_PAD_TO 0x20000
236 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
237 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
240 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
241 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
242 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
243 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
244 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
245 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
246 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
247 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
248 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
249 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
250 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
251 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
252 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
253 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
254 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
255 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
256 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
257 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
258 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
259 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
260 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
261 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
262 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
263 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
264 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
265 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
266 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
268 #ifndef CONFIG_QSPI_BOOT
269 #define CONFIG_ENV_IS_IN_FLASH
270 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
271 #define CONFIG_ENV_SECT_SIZE 0x20000
272 #define CONFIG_ENV_SIZE 0x2000
276 /* Debug Server firmware */
277 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
278 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
280 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
285 #define I2C_MUX_PCA_ADDR 0x77
286 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
288 /* I2C bus multiplexer */
289 #define I2C_MUX_CH_DEFAULT 0x8
292 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
293 #define CONFIG_SPI_FLASH
295 #ifdef CONFIG_FSL_DSPI
296 #define CONFIG_SPI_FLASH_STMICRO
297 #define CONFIG_SPI_FLASH_SST
298 #define CONFIG_SPI_FLASH_EON
301 #ifdef CONFIG_FSL_QSPI
302 #define CONFIG_SPI_FLASH_SPANSION
303 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */
304 #define FSL_QSPI_FLASH_NUM 4
307 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
308 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
309 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
311 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
319 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
320 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
327 #define CONFIG_RTC_DS3231 1
328 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
331 #define CONFIG_ID_EEPROM
332 #define CONFIG_SYS_I2C_EEPROM_NXID
333 #define CONFIG_SYS_EEPROM_BUS_NUM 0
334 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
335 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
336 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
337 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
339 #define CONFIG_FSL_MEMAC
342 #define CONFIG_PCI_SCAN_SHOW
343 #define CONFIG_CMD_PCI
348 #define CONFIG_FSL_ESDHC
349 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
352 /* Initial environment variables */
353 #undef CONFIG_EXTRA_ENV_SETTINGS
354 #ifdef CONFIG_SECURE_BOOT
355 #define CONFIG_EXTRA_ENV_SETTINGS \
356 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
357 "loadaddr=0x80100000\0" \
358 "kernel_addr=0x100000\0" \
359 "ramdisk_addr=0x800000\0" \
360 "ramdisk_size=0x2000000\0" \
361 "fdt_high=0xa0000000\0" \
362 "initrd_high=0xffffffffffffffff\0" \
363 "kernel_start=0x581000000\0" \
364 "kernel_load=0xa0000000\0" \
365 "kernel_size=0x2800000\0" \
366 "mcmemsize=0x40000000\0" \
367 "mcinitcmd=esbc_validate 0x580700000;" \
368 "esbc_validate 0x580740000;" \
369 "fsl_mc start mc 0x580a00000" \
372 #define CONFIG_EXTRA_ENV_SETTINGS \
373 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
374 "loadaddr=0x80100000\0" \
375 "kernel_addr=0x100000\0" \
376 "ramdisk_addr=0x800000\0" \
377 "ramdisk_size=0x2000000\0" \
378 "fdt_high=0xa0000000\0" \
379 "initrd_high=0xffffffffffffffff\0" \
380 "kernel_start=0x581000000\0" \
381 "kernel_load=0xa0000000\0" \
382 "kernel_size=0x2800000\0" \
383 "mcmemsize=0x40000000\0" \
384 "mcinitcmd=fsl_mc start mc 0x580a00000" \
386 #endif /* CONFIG_SECURE_BOOT */
389 #ifdef CONFIG_FSL_MC_ENET
390 #define CONFIG_FSL_MEMAC
391 #define CONFIG_PHYLIB
392 #define CONFIG_PHYLIB_10G
393 #define CONFIG_PHY_VITESSE
394 #define CONFIG_PHY_REALTEK
395 #define CONFIG_PHY_TERANETICS
396 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
397 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
398 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
399 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
401 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
402 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
403 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
404 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
405 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
406 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
407 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
408 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
409 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
410 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
411 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
412 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
413 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
414 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
415 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
416 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
418 #define CONFIG_MII /* MII PHY management */
419 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
420 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
427 #define CONFIG_HAS_FSL_XHCI_USB
428 #define CONFIG_USB_XHCI_FSL
429 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
430 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
432 #include <asm/fsl_secure_boot.h>
434 #endif /* __LS2_QDS_H */