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1 /*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __LS2_QDS_H
8 #define __LS2_QDS_H
9
10 #include "ls2080a_common.h"
11
12 #ifndef __ASSEMBLY__
13 unsigned long get_board_sys_clk(void);
14 unsigned long get_board_ddr_clk(void);
15 #endif
16
17 #ifdef CONFIG_FSL_QSPI
18 #define CONFIG_SYS_NO_FLASH
19 #undef CONFIG_CMD_IMLS
20 #define CONFIG_QIXIS_I2C_ACCESS
21 #define CONFIG_SYS_I2C_EARLY_INIT
22 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
23 #endif
24
25 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
26 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
27 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
28 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
29
30 #define CONFIG_DDR_SPD
31 #define CONFIG_DDR_ECC
32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
34 #define SPD_EEPROM_ADDRESS1 0x51
35 #define SPD_EEPROM_ADDRESS2 0x52
36 #define SPD_EEPROM_ADDRESS3 0x53
37 #define SPD_EEPROM_ADDRESS4 0x54
38 #define SPD_EEPROM_ADDRESS5 0x55
39 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
40 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
41 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
42 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
43 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
46 #endif
47 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
48
49 /* SATA */
50 #define CONFIG_LIBATA
51 #define CONFIG_SCSI_AHCI
52 #define CONFIG_SCSI_AHCI_PLAT
53 #define CONFIG_SCSI
54
55 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
56 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
57
58 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
59 #define CONFIG_SYS_SCSI_MAX_LUN 1
60 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
61 CONFIG_SYS_SCSI_MAX_LUN)
62 #define CONFIG_PARTITION_UUIDS
63 #define CONFIG_EFI_PARTITION
64 #define CONFIG_CMD_GPT
65
66 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
67
68 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
69 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
70 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
71
72 #define CONFIG_SYS_NOR0_CSPR \
73 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
74 CSPR_PORT_SIZE_16 | \
75 CSPR_MSEL_NOR | \
76 CSPR_V)
77 #define CONFIG_SYS_NOR0_CSPR_EARLY \
78 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
79 CSPR_PORT_SIZE_16 | \
80 CSPR_MSEL_NOR | \
81 CSPR_V)
82 #define CONFIG_SYS_NOR1_CSPR \
83 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
84 CSPR_PORT_SIZE_16 | \
85 CSPR_MSEL_NOR | \
86 CSPR_V)
87 #define CONFIG_SYS_NOR1_CSPR_EARLY \
88 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
89 CSPR_PORT_SIZE_16 | \
90 CSPR_MSEL_NOR | \
91 CSPR_V)
92 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
93 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
94 FTIM0_NOR_TEADC(0x5) | \
95 FTIM0_NOR_TEAHC(0x5))
96 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
97 FTIM1_NOR_TRAD_NOR(0x1a) |\
98 FTIM1_NOR_TSEQRAD_NOR(0x13))
99 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
100 FTIM2_NOR_TCH(0x4) | \
101 FTIM2_NOR_TWPH(0x0E) | \
102 FTIM2_NOR_TWP(0x1c))
103 #define CONFIG_SYS_NOR_FTIM3 0x04000000
104 #define CONFIG_SYS_IFC_CCR 0x01000000
105
106 #ifndef CONFIG_SYS_NO_FLASH
107 #define CONFIG_FLASH_CFI_DRIVER
108 #define CONFIG_SYS_FLASH_CFI
109 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
110 #define CONFIG_SYS_FLASH_QUIET_TEST
111 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
112
113 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
114 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
115 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
116 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
117
118 #define CONFIG_SYS_FLASH_EMPTY_INFO
119 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
120 CONFIG_SYS_FLASH_BASE + 0x40000000}
121 #endif
122
123 #define CONFIG_NAND_FSL_IFC
124 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
125 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
126
127 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
128 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
129 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
130 | CSPR_MSEL_NAND /* MSEL = NAND */ \
131 | CSPR_V)
132 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
133
134 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
135 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
136 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
137 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
138 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
139 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
140 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
141
142 #define CONFIG_SYS_NAND_ONFI_DETECTION
143
144 /* ONFI NAND Flash mode0 Timing Params */
145 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
146 FTIM0_NAND_TWP(0x18) | \
147 FTIM0_NAND_TWCHT(0x07) | \
148 FTIM0_NAND_TWH(0x0a))
149 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
150 FTIM1_NAND_TWBE(0x39) | \
151 FTIM1_NAND_TRR(0x0e) | \
152 FTIM1_NAND_TRP(0x18))
153 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
154 FTIM2_NAND_TREH(0x0a) | \
155 FTIM2_NAND_TWHRE(0x1e))
156 #define CONFIG_SYS_NAND_FTIM3 0x0
157
158 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
159 #define CONFIG_SYS_MAX_NAND_DEVICE 1
160 #define CONFIG_MTD_NAND_VERIFY_WRITE
161 #define CONFIG_CMD_NAND
162
163 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
164
165 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
166 #define QIXIS_LBMAP_SWITCH 0x06
167 #define QIXIS_LBMAP_MASK 0x0f
168 #define QIXIS_LBMAP_SHIFT 0
169 #define QIXIS_LBMAP_DFLTBANK 0x00
170 #define QIXIS_LBMAP_ALTBANK 0x04
171 #define QIXIS_LBMAP_NAND 0x09
172 #define QIXIS_LBMAP_QSPI 0x0f
173 #define QIXIS_RST_CTL_RESET 0x31
174 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
175 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
176 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
177 #define QIXIS_RCW_SRC_NAND 0x107
178 #define QIXIS_RCW_SRC_QSPI 0x62
179 #define QIXIS_RST_FORCE_MEM 0x01
180
181 #define CONFIG_SYS_CSPR3_EXT (0x0)
182 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
183 | CSPR_PORT_SIZE_8 \
184 | CSPR_MSEL_GPCM \
185 | CSPR_V)
186 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
187 | CSPR_PORT_SIZE_8 \
188 | CSPR_MSEL_GPCM \
189 | CSPR_V)
190
191 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
192 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
193 /* QIXIS Timing parameters for IFC CS3 */
194 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
195 FTIM0_GPCM_TEADC(0x0e) | \
196 FTIM0_GPCM_TEAHC(0x0e))
197 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
198 FTIM1_GPCM_TRAD(0x3f))
199 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
200 FTIM2_GPCM_TCH(0xf) | \
201 FTIM2_GPCM_TWP(0x3E))
202 #define CONFIG_SYS_CS3_FTIM3 0x0
203
204 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
205 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
206 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
207 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
208 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
209 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
210 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
211 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
212 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
213 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
214 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
215 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
216 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
217 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
218 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
219 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
220 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
221 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
222 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
223 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
224 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
225 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
226 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
227 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
228 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
229 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
230 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
231 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
232
233 #define CONFIG_ENV_IS_IN_NAND
234 #define CONFIG_ENV_OFFSET (896 * 1024)
235 #define CONFIG_ENV_SECT_SIZE 0x20000
236 #define CONFIG_ENV_SIZE 0x2000
237 #define CONFIG_SPL_PAD_TO 0x20000
238 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
239 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
240 #else
241 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
242 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
243 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
244 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
245 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
246 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
247 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
248 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
249 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
250 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
251 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
252 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
253 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
254 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
255 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
256 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
257 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
258 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
259 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
260 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
261 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
262 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
263 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
264 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
265 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
266 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
267 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
268
269 #if defined(CONFIG_QSPI_BOOT)
270 #define CONFIG_SYS_TEXT_BASE 0x20010000
271 #define CONFIG_ENV_IS_IN_SPI_FLASH
272 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
273 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
274 #define CONFIG_ENV_SECT_SIZE 0x10000
275 #else
276 #define CONFIG_ENV_IS_IN_FLASH
277 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
278 #define CONFIG_ENV_SECT_SIZE 0x20000
279 #define CONFIG_ENV_SIZE 0x2000
280 #endif
281 #endif
282
283 /* Debug Server firmware */
284 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
285 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
286
287 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
288
289 /*
290 * I2C
291 */
292 #define I2C_MUX_PCA_ADDR 0x77
293 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
294
295 /* I2C bus multiplexer */
296 #define I2C_MUX_CH_DEFAULT 0x8
297
298 /* SPI */
299 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
300 #define CONFIG_SPI_FLASH
301
302 #ifdef CONFIG_FSL_DSPI
303 #define CONFIG_SPI_FLASH_STMICRO
304 #define CONFIG_SPI_FLASH_SST
305 #define CONFIG_SPI_FLASH_EON
306 #endif
307
308 #ifdef CONFIG_FSL_QSPI
309 #define CONFIG_SPI_FLASH_SPANSION
310 #define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */
311 #define FSL_QSPI_FLASH_NUM 4
312 #endif
313 /*
314 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
315 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
316 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
317 */
318 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
319
320 #endif
321
322 /*
323 * MMC
324 */
325 #ifdef CONFIG_MMC
326 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
327 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
328 #endif
329
330 /*
331 * RTC configuration
332 */
333 #define RTC
334 #define CONFIG_RTC_DS3231 1
335 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
336 #define CONFIG_CMD_DATE
337
338 /* EEPROM */
339 #define CONFIG_ID_EEPROM
340 #define CONFIG_CMD_EEPROM
341 #define CONFIG_SYS_I2C_EEPROM_NXID
342 #define CONFIG_SYS_EEPROM_BUS_NUM 0
343 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
344 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
345 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
346 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
347
348 #define CONFIG_FSL_MEMAC
349
350 #ifdef CONFIG_PCI
351 #define CONFIG_PCI_SCAN_SHOW
352 #define CONFIG_CMD_PCI
353 #endif
354
355 /* MMC */
356 #ifdef CONFIG_MMC
357 #define CONFIG_FSL_ESDHC
358 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
359 #define CONFIG_GENERIC_MMC
360 #endif
361
362 /* Initial environment variables */
363 #undef CONFIG_EXTRA_ENV_SETTINGS
364 #ifdef CONFIG_SECURE_BOOT
365 #define CONFIG_EXTRA_ENV_SETTINGS \
366 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
367 "loadaddr=0x80100000\0" \
368 "kernel_addr=0x100000\0" \
369 "ramdisk_addr=0x800000\0" \
370 "ramdisk_size=0x2000000\0" \
371 "fdt_high=0xa0000000\0" \
372 "initrd_high=0xffffffffffffffff\0" \
373 "kernel_start=0x581100000\0" \
374 "kernel_load=0xa0000000\0" \
375 "kernel_size=0x2800000\0" \
376 "mcinitcmd=esbc_validate 0x580c80000;" \
377 "esbc_validate 0x580cc0000;" \
378 "fsl_mc start mc 0x580300000" \
379 " 0x580800000 \0"
380 #else
381 #define CONFIG_EXTRA_ENV_SETTINGS \
382 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
383 "loadaddr=0x80100000\0" \
384 "kernel_addr=0x100000\0" \
385 "ramdisk_addr=0x800000\0" \
386 "ramdisk_size=0x2000000\0" \
387 "fdt_high=0xa0000000\0" \
388 "initrd_high=0xffffffffffffffff\0" \
389 "kernel_start=0x581100000\0" \
390 "kernel_load=0xa0000000\0" \
391 "kernel_size=0x2800000\0" \
392 "mcinitcmd=fsl_mc start mc 0x580300000" \
393 " 0x580800000 \0"
394 #endif /* CONFIG_SECURE_BOOT */
395
396
397 #ifdef CONFIG_FSL_MC_ENET
398 #define CONFIG_FSL_MEMAC
399 #define CONFIG_PHYLIB
400 #define CONFIG_PHYLIB_10G
401 #define CONFIG_PHY_VITESSE
402 #define CONFIG_PHY_REALTEK
403 #define CONFIG_PHY_TERANETICS
404 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
405 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
406 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
407 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
408
409 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
410 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
411 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
412 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
413 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
414 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
415 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
416 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
417 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
418 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
419 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
420 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
421 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
422 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
423 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
424 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
425
426 #define CONFIG_MII /* MII PHY management */
427 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
428 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
429
430 #endif
431
432 /*
433 * USB
434 */
435 #define CONFIG_HAS_FSL_XHCI_USB
436 #define CONFIG_USB_XHCI_FSL
437 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
438 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
439
440 #include <asm/fsl_secure_boot.h>
441
442 #endif /* __LS2_QDS_H */