include/configs/ls2080ardb.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #undef CONFIG_CONS_INDEX
  13 #define CONFIG_CONS_INDEX       2
  14
  15 #define CONFIG_DISPLAY_BOARDINFO
  16
  17 #define I2C_MUX_CH_VOL_MONITOR          0xa
  18 #define I2C_VOL_MONITOR_ADDR            0x38
  19 #define CONFIG_VOL_MONITOR_IR36021_READ
  20 #define CONFIG_VOL_MONITOR_IR36021_SET
  21
  22 #define CONFIG_VID_FLS_ENV              "ls2080ardb_vdd_mv"
  23 #ifndef CONFIG_SPL_BUILD
  24 #define CONFIG_VID
  25 #endif
  26 /* step the IR regulator in 5mV increments */
  27 #define IR_VDD_STEP_DOWN                5
  28 #define IR_VDD_STEP_UP                  5
  29 /* The lowest and highest voltage allowed for LS2080ARDB */
  30 #define VDD_MV_MIN                      819
  31 #define VDD_MV_MAX                      1212
  32
  33 #ifndef __ASSEMBLY__
  34 unsigned long get_board_sys_clk(void);
  35 #endif
  36
  37 #define CONFIG_SYS_FSL_CLK
  38 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  39 #define CONFIG_DDR_CLK_FREQ             133333333
  40 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  41
  42 #define CONFIG_DDR_SPD
  43 #define CONFIG_DDR_ECC
  44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  45 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  46 #define SPD_EEPROM_ADDRESS1     0x51
  47 #define SPD_EEPROM_ADDRESS2     0x52
  48 #define SPD_EEPROM_ADDRESS3     0x53
  49 #define SPD_EEPROM_ADDRESS4     0x54
  50 #define SPD_EEPROM_ADDRESS5     0x55
  51 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  52 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  53 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  54 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  55 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  56 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  57 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  58 #endif
  59 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  60
  61 /* SATA */
  62 #define CONFIG_LIBATA
  63 #define CONFIG_SCSI_AHCI
  64 #define CONFIG_SCSI_AHCI_PLAT
  65 #define CONFIG_CMD_SCSI
  66 #define CONFIG_DOS_PARTITION
  67 #define CONFIG_BOARD_LATE_INIT
  68
  69 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  70 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  71
  72 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  73 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  74 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  75                                                 CONFIG_SYS_SCSI_MAX_LUN)
  76
  77 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  78
  79 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  80 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  81 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  82
  83 #define CONFIG_SYS_NOR0_CSPR                                    \
  84         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  85         CSPR_PORT_SIZE_16                                       | \
  86         CSPR_MSEL_NOR                                           | \
  87         CSPR_V)
  88 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  89         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  90         CSPR_PORT_SIZE_16                                       | \
  91         CSPR_MSEL_NOR                                           | \
  92         CSPR_V)
  93 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  94 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  95                                 FTIM0_NOR_TEADC(0x5) | \
  96                                 FTIM0_NOR_TEAHC(0x5))
  97 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  98                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  99                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 100 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 101                                 FTIM2_NOR_TCH(0x4) | \
 102                                 FTIM2_NOR_TWPH(0x0E) | \
 103                                 FTIM2_NOR_TWP(0x1c))
 104 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 105 #define CONFIG_SYS_IFC_CCR      0x01000000
 106
 107 #ifndef CONFIG_SYS_NO_FLASH
 108 #define CONFIG_FLASH_CFI_DRIVER
 109 #define CONFIG_SYS_FLASH_CFI
 110 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 111 #define CONFIG_SYS_FLASH_QUIET_TEST
 112 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 113
 114 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 115 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 116 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 117 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 118
 119 #define CONFIG_SYS_FLASH_EMPTY_INFO
 120 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 121                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 122 #endif
 123
 124 #define CONFIG_NAND_FSL_IFC
 125 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 126 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 127
 128 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 129 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 130                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 131                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 132                                 | CSPR_V)
 133 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 134
 135 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 136                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 137                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 138                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 139                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 140                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 141                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 142
 143 #define CONFIG_SYS_NAND_ONFI_DETECTION
 144
 145 /* ONFI NAND Flash mode0 Timing Params */
 146 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 147                                         FTIM0_NAND_TWP(0x30)   | \
 148                                         FTIM0_NAND_TWCHT(0x0e) | \
 149                                         FTIM0_NAND_TWH(0x14))
 150 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 151                                         FTIM1_NAND_TWBE(0xab)  | \
 152                                         FTIM1_NAND_TRR(0x1c)   | \
 153                                         FTIM1_NAND_TRP(0x30))
 154 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 155                                         FTIM2_NAND_TREH(0x14) | \
 156                                         FTIM2_NAND_TWHRE(0x3c))
 157 #define CONFIG_SYS_NAND_FTIM3           0x0
 158
 159 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 160 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 161 #define CONFIG_MTD_NAND_VERIFY_WRITE
 162 #define CONFIG_CMD_NAND
 163
 164 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 165
 166 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 167 #define QIXIS_LBMAP_SWITCH              0x06
 168 #define QIXIS_LBMAP_MASK                0x0f
 169 #define QIXIS_LBMAP_SHIFT               0
 170 #define QIXIS_LBMAP_DFLTBANK            0x00
 171 #define QIXIS_LBMAP_ALTBANK             0x04
 172 #define QIXIS_LBMAP_NAND                0x09
 173 #define QIXIS_RST_CTL_RESET             0x31
 174 #define QIXIS_RST_CTL_RESET_EN          0x30
 175 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 176 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 177 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 178 #define QIXIS_RCW_SRC_NAND              0x119
 179 #define QIXIS_RST_FORCE_MEM             0x01
 180
 181 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 182 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 183                                 | CSPR_PORT_SIZE_8 \
 184                                 | CSPR_MSEL_GPCM \
 185                                 | CSPR_V)
 186 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 187                                 | CSPR_PORT_SIZE_8 \
 188                                 | CSPR_MSEL_GPCM \
 189                                 | CSPR_V)
 190
 191 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 192 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 193 /* QIXIS Timing parameters for IFC CS3 */
 194 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 195                                         FTIM0_GPCM_TEADC(0x0e) | \
 196                                         FTIM0_GPCM_TEAHC(0x0e))
 197 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 198                                         FTIM1_GPCM_TRAD(0x3f))
 199 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 200                                         FTIM2_GPCM_TCH(0xf) | \
 201                                         FTIM2_GPCM_TWP(0x3E))
 202 #define CONFIG_SYS_CS3_FTIM3            0x0
 203
 204 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
 205 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 206 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 207 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 208 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 209 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 210 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 211 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 212 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 213 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 214 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 215 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 216 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 217 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 218 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 219 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 220 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 221 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 222
 223 #define CONFIG_ENV_IS_IN_NAND
 224 #define CONFIG_ENV_OFFSET               (2048 * 1024)
 225 #define CONFIG_ENV_SECT_SIZE            0x20000
 226 #define CONFIG_ENV_SIZE                 0x2000
 227 #define CONFIG_SPL_PAD_TO               0x80000
 228 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
 229 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 230 #else
 231 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 232 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 233 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 234 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 235 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 236 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 237 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 238 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 239 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 240 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 241 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 242 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 243 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 244 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 245 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 246 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 247 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 248
 249 #define CONFIG_ENV_IS_IN_FLASH
 250 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 251 #define CONFIG_ENV_SECT_SIZE            0x20000
 252 #define CONFIG_ENV_SIZE                 0x2000
 253 #endif
 254
 255 /* Debug Server firmware */
 256 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 257 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 258
 259 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 260
 261 /*
 262  * I2C
 263  */
 264 #define I2C_MUX_PCA_ADDR                0x75
 265 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 266
 267 /* I2C bus multiplexer */
 268 #define I2C_MUX_CH_DEFAULT      0x8
 269
 270 /* SPI */
 271 #ifdef CONFIG_FSL_DSPI
 272 #define CONFIG_SPI_FLASH
 273 #define CONFIG_SPI_FLASH_BAR
 274 #endif
 275
 276 /*
 277  * RTC configuration
 278  */
 279 #define RTC
 280 #define CONFIG_RTC_DS3231               1
 281 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 282 #define CONFIG_CMD_DATE
 283
 284 /* EEPROM */
 285 #define CONFIG_ID_EEPROM
 286 #define CONFIG_CMD_EEPROM
 287 #define CONFIG_SYS_I2C_EEPROM_NXID
 288 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 289 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 290 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 291 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 292 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 293
 294 #define CONFIG_FSL_MEMAC
 295 #define CONFIG_PCI              /* Enable PCIE */
 296 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 297
 298 #ifdef CONFIG_PCI
 299 #define CONFIG_PCI_PNP
 300 #define CONFIG_PCI_SCAN_SHOW
 301 #define CONFIG_CMD_PCI
 302 #endif
 303
 304 /*  MMC  */
 305 #define CONFIG_MMC
 306 #ifdef CONFIG_MMC
 307 #define CONFIG_FSL_ESDHC
 308 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 309 #define CONFIG_GENERIC_MMC
 310 #define CONFIG_DOS_PARTITION
 311 #endif
 312
 313 #define CONFIG_MISC_INIT_R
 314
 315 /*
 316  * USB
 317  */
 318 #define CONFIG_HAS_FSL_XHCI_USB
 319 #define CONFIG_USB_XHCI
 320 #define CONFIG_USB_XHCI_FSL
 321 #define CONFIG_USB_XHCI_DWC3
 322 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 323 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 324 #define CONFIG_USB_STORAGE
 325
 326 /* Initial environment variables */
 327 #undef CONFIG_EXTRA_ENV_SETTINGS
 328 #define CONFIG_EXTRA_ENV_SETTINGS               \
 329         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 330         "loadaddr=0x80100000\0"                 \
 331         "kernel_addr=0x100000\0"                \
 332         "ramdisk_addr=0x800000\0"               \
 333         "ramdisk_size=0x2000000\0"              \
 334         "fdt_high=0xa0000000\0"                 \
 335         "initrd_high=0xffffffffffffffff\0"      \
 336         "kernel_start=0x581100000\0"            \
 337         "kernel_load=0xa0000000\0"              \
 338         "kernel_size=0x2800000\0"               \
 339         "mcinitcmd=fsl_mc start mc 0x580300000" \
 340         " 0x580800000 \0"
 341
 342 #undef CONFIG_BOOTARGS
 343 #define CONFIG_BOOTARGS         "console=ttyS1,115200 root=/dev/ram0 " \
 344                                 "earlycon=uart8250,mmio,0x21c0600 " \
 345                                 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
 346                                 " hugepagesz=2m hugepages=256"
 347
 348 /* MAC/PHY configuration */
 349 #ifdef CONFIG_FSL_MC_ENET
 350 #define CONFIG_PHYLIB_10G
 351 #define CONFIG_PHY_AQUANTIA
 352 #define CONFIG_PHY_CORTINA
 353 #define CONFIG_PHYLIB
 354 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 355 #define CONFIG_CORTINA_FW_ADDR          0x581000000
 356 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 357
 358 #define CORTINA_PHY_ADDR1       0x10
 359 #define CORTINA_PHY_ADDR2       0x11
 360 #define CORTINA_PHY_ADDR3       0x12
 361 #define CORTINA_PHY_ADDR4       0x13
 362 #define AQ_PHY_ADDR1            0x00
 363 #define AQ_PHY_ADDR2            0x01
 364 #define AQ_PHY_ADDR3            0x02
 365 #define AQ_PHY_ADDR4            0x03
 366 #define AQR405_IRQ_MASK         0x36
 367
 368 #define CONFIG_MII
 369 #define CONFIG_ETHPRIME         "DPNI1"
 370 #define CONFIG_PHY_GIGE
 371 #define CONFIG_PHY_AQUANTIA
 372 #endif
 373
 374 #include <asm/fsl_secure_boot.h>
 375
 376 #endif /* __LS2_RDB_H */