include/configs/ls2085a_common.h

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_COMMON_H
   8 #define __LS2_COMMON_H
   9
  10 #define CONFIG_SYS_GENERIC_BOARD
  11
  12 #define CONFIG_REMAKE_ELF
  13 #define CONFIG_FSL_LSCH3
  14 #define CONFIG_LS2085A
  15 #define CONFIG_GICV3
  16 #define CONFIG_FSL_TZPC_BP147
  17
  18 /* Errata fixes */
  19 #define CONFIG_ARM_ERRATA_828024
  20 #define CONFIG_ARM_ERRATA_826974
  21
  22 #include <asm/arch-fsl-lsch3/config.h>
  23 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
  24 #define CONFIG_SYS_HAS_SERDES
  25 #endif
  26
  27 /* We need architecture specific misc initializations */
  28 #define CONFIG_ARCH_MISC_INIT
  29
  30 /* Link Definitions */
  31 #ifdef CONFIG_SPL
  32 #define CONFIG_SYS_TEXT_BASE            0x80400000
  33 #else
  34 #define CONFIG_SYS_TEXT_BASE            0x30100000
  35 #endif
  36
  37 #ifdef CONFIG_EMU
  38 #define CONFIG_SYS_NO_FLASH
  39 #endif
  40
  41 #define CONFIG_SUPPORT_RAW_INITRD
  42
  43 #define CONFIG_SKIP_LOWLEVEL_INIT
  44 #define CONFIG_BOARD_EARLY_INIT_F       1
  45
  46 /* Flat Device Tree Definitions */
  47 #define CONFIG_OF_LIBFDT
  48 #define CONFIG_OF_BOARD_SETUP
  49
  50 /* new uImage format support */
  51 #define CONFIG_FIT
  52 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  53
  54 #ifndef CONFIG_SPL
  55 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  56 #endif
  57 #ifndef CONFIG_SYS_FSL_DDR4
  58 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  59 #define CONFIG_SYS_DDR_RAW_TIMING
  60 #endif
  61
  62 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  63
  64 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  65 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  66 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  67 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  68 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       2
  69
  70 /*
  71  * SMP Definitinos
  72  */
  73 #define CPU_RELEASE_ADDR                secondary_boot_func
  74
  75 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
  76 #define CONFIG_SYS_DP_DDR_BASE          0x6000000000ULL
  77 /*
  78  * DDR controller use 0 as the base address for binding.
  79  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  80  */
  81 #define CONFIG_SYS_DP_DDR_BASE_PHY      0
  82 #define CONFIG_DP_DDR_CTRL              2
  83 #define CONFIG_DP_DDR_NUM_CTRLS         1
  84
  85 /* Generic Timer Definitions */
  86 /*
  87  * This is not an accurate number. It is used in start.S. The frequency
  88  * will be udpated later when get_bus_freq(0) is available.
  89  */
  90 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  91
  92 /* Size of malloc() pool */
  93 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 2048 * 1024)
  94
  95 /* I2C */
  96 #define CONFIG_CMD_I2C
  97 #define CONFIG_SYS_I2C
  98 #define CONFIG_SYS_I2C_MXC
  99 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 100 #define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
 101
 102 /* Serial Port */
 103 #define CONFIG_CONS_INDEX       1
 104 #define CONFIG_SYS_NS16550
 105 #define CONFIG_SYS_NS16550_SERIAL
 106 #define CONFIG_SYS_NS16550_REG_SIZE     1
 107 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 108
 109 #define CONFIG_BAUDRATE                 115200
 110 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 111
 112 /* IFC */
 113 #define CONFIG_FSL_IFC
 114
 115 /*
 116  * During booting, IFC is mapped at the region of 0x30000000.
 117  * But this region is limited to 256MB. To accommodate NOR, promjet
 118  * and FPGA. This region is divided as below:
 119  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 120  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 121  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 122  *
 123  * To accommodate bigger NOR flash and other devices, we will map IFC
 124  * chip selects to as below:
 125  * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
 126  * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
 127  * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
 128  * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
 129  * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
 130  *
 131  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 132  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 133  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 134  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 135  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 136  */
 137
 138 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
 139 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
 140 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 141
 142 #define CONFIG_SYS_FLASH1_BASE_PHYS             0xC0000000
 143 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY       0x8000000
 144
 145 #ifndef CONFIG_SYS_NO_FLASH
 146 #define CONFIG_FLASH_CFI_DRIVER
 147 #define CONFIG_SYS_FLASH_CFI
 148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 149 #define CONFIG_SYS_FLASH_QUIET_TEST
 150 #endif
 151
 152 #ifndef __ASSEMBLY__
 153 unsigned long long get_qixis_addr(void);
 154 #endif
 155 #define QIXIS_BASE                              get_qixis_addr()
 156 #define QIXIS_BASE_PHYS                         0x20000000
 157 #define QIXIS_BASE_PHYS_EARLY                   0xC000000
 158 #define QIXIS_STAT_PRES1                        0xb
 159 #define QIXIS_SDID_MASK                         0x07
 160 #define QIXIS_ESDHC_NO_ADAPTER                  0x7
 161
 162 #define CONFIG_SYS_NAND_BASE                    0x530000000ULL
 163 #define CONFIG_SYS_NAND_BASE_PHYS               0x30000000
 164
 165 /* Debug Server firmware */
 166 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE     (512UL * 1024 * 1024)
 167 /* 2 sec timeout */
 168 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT                 (2 * 1000 * 1000)
 169
 170 /* MC firmware */
 171 #define CONFIG_FSL_MC_ENET
 172 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE    (512UL * 1024 * 1024)
 173 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 174 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH     0x20000
 175 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 176 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH     0x20000
 177 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 178
 179 /* Carve out a DDR region which will not be used by u-boot/Linux */
 180 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
 181 #define CONFIG_SYS_MEM_TOP_HIDE         get_dram_size_to_hide()
 182 #endif
 183
 184 /* PCIe */
 185 #define CONFIG_PCIE1            /* PCIE controler 1 */
 186 #define CONFIG_PCIE2            /* PCIE controler 2 */
 187 #define CONFIG_PCIE3            /* PCIE controler 3 */
 188 #define CONFIG_PCIE4            /* PCIE controler 4 */
 189 #define FSL_PCIE_COMPAT "fsl,20851a-pcie"
 190
 191 #define CONFIG_SYS_PCI_64BIT
 192
 193 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 194 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 195 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 196 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 197
 198 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 199 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 200 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 201
 202 #define CONFIG_SYS_PCIE_MEM_BUS         0x40000000
 203 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x40000000
 204 #define CONFIG_SYS_PCIE_MEM_SIZE        0x40000000      /* 1G */
 205
 206 /* Command line configuration */
 207 #define CONFIG_CMD_CACHE
 208 #define CONFIG_CMD_BDI
 209 #define CONFIG_CMD_DHCP
 210 #define CONFIG_CMD_ENV
 211 #define CONFIG_CMD_FLASH
 212 #define CONFIG_CMD_IMI
 213 #define CONFIG_CMD_LOADB
 214 #define CONFIG_CMD_MEMORY
 215 #define CONFIG_CMD_MII
 216 #define CONFIG_CMD_NET
 217 #define CONFIG_CMD_PING
 218 #define CONFIG_CMD_SAVEENV
 219 #define CONFIG_CMD_RUN
 220 #define CONFIG_CMD_BOOTD
 221 #define CONFIG_CMD_ECHO
 222 #define CONFIG_CMD_SOURCE
 223
 224 /* Miscellaneous configurable options */
 225 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 226 #define CONFIG_ARCH_EARLY_INIT_R
 227
 228 /* Physical Memory Map */
 229 /* fixme: these need to be checked against the board */
 230 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 231
 232 #define CONFIG_NR_DRAM_BANKS            3
 233
 234 #define CONFIG_HWCONFIG
 235 #define HWCONFIG_BUFFER_SIZE            128
 236
 237 #define CONFIG_DISPLAY_CPUINFO
 238
 239 /* Initial environment variables */
 240 #define CONFIG_EXTRA_ENV_SETTINGS               \
 241         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 242         "loadaddr=0x80100000\0"                 \
 243         "kernel_addr=0x100000\0"                \
 244         "ramdisk_addr=0x800000\0"               \
 245         "ramdisk_size=0x2000000\0"              \
 246         "fdt_high=0xa0000000\0"                 \
 247         "initrd_high=0xffffffffffffffff\0"      \
 248         "kernel_start=0x581200000\0"            \
 249         "kernel_load=0xa0000000\0"              \
 250         "kernel_size=0x1000000\0"               \
 251         "console=ttyAMA0,38400n8\0"
 252
 253 #define CONFIG_BOOTARGS         "console=ttyS1,115200 root=/dev/ram0 " \
 254                                 "earlycon=uart8250,mmio,0x21c0600,115200 " \
 255                                 "default_hugepagesz=2m hugepagesz=2m " \
 256                                 "hugepages=16"
 257 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 258                                         "$kernel_size && bootm $kernel_load"
 259 #define CONFIG_BOOTDELAY                10
 260
 261 /* Monitor Command Prompt */
 262 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 263 #define CONFIG_SYS_PROMPT               "=> "
 264 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 265                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 266 #define CONFIG_SYS_HUSH_PARSER
 267 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 268 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 269 #define CONFIG_SYS_LONGHELP
 270 #define CONFIG_CMDLINE_EDITING          1
 271 #define CONFIG_AUTO_COMPLETE
 272 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 273
 274 #ifndef __ASSEMBLY__
 275 unsigned long get_dram_size_to_hide(void);
 276 #endif
 277
 278 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 279
 280 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 281 #define CONFIG_SPL_BSS_MAX_SIZE         0x00100000
 282 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 283 #define CONFIG_SPL_ENV_SUPPORT
 284 #define CONFIG_SPL_FRAMEWORK
 285 #define CONFIG_SPL_I2C_SUPPORT
 286 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
 287 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 288 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 289 #define CONFIG_SPL_MAX_SIZE             0x16000
 290 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 291 #define CONFIG_SPL_NAND_SUPPORT
 292 #define CONFIG_SPL_SERIAL_SUPPORT
 293 #define CONFIG_SPL_STACK                (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
 294 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 295 #define CONFIG_SPL_TEXT_BASE            0x1800a000
 296
 297 #define CONFIG_SYS_NAND_U_BOOT_DST      0x80400000
 298 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 299 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x00100000
 300 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 301 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 302
 303 #endif /* __LS2_COMMON_H */