include/configs/ls2085aqds.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2085a_common.h"
  11 #include <config_cmd_default.h>
  12
  13 #define CONFIG_IDENT_STRING             " LS2085A-QDS"
  14 #define CONFIG_BOOTP_VCI_STRING         "U-boot.LS2085A-QDS"
  15
  16 #define CONFIG_DISPLAY_BOARDINFO
  17
  18 #ifndef __ASSEMBLY__
  19 unsigned long get_board_sys_clk(void);
  20 unsigned long get_board_ddr_clk(void);
  21 #endif
  22
  23 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  24 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  25 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  26
  27 #define CONFIG_DDR_SPD
  28 #define CONFIG_DDR_ECC
  29 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  30 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  31 #define SPD_EEPROM_ADDRESS1     0x51
  32 #define SPD_EEPROM_ADDRESS2     0x52
  33 #define SPD_EEPROM_ADDRESS3     0x53
  34 #define SPD_EEPROM_ADDRESS4     0x54
  35 #define SPD_EEPROM_ADDRESS5     0x55
  36 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  37 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  38 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  39 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  40 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  41 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  42 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  43
  44 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  45
  46 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  47 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  48 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  49
  50 #define CONFIG_SYS_NOR0_CSPR                                    \
  51         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  52         CSPR_PORT_SIZE_16                                       | \
  53         CSPR_MSEL_NOR                                           | \
  54         CSPR_V)
  55 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  56         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  57         CSPR_PORT_SIZE_16                                       | \
  58         CSPR_MSEL_NOR                                           | \
  59         CSPR_V)
  60 #define CONFIG_SYS_NOR1_CSPR                                    \
  61         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  62         CSPR_PORT_SIZE_16                                       | \
  63         CSPR_MSEL_NOR                                           | \
  64         CSPR_V)
  65 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  66         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  67         CSPR_PORT_SIZE_16                                       | \
  68         CSPR_MSEL_NOR                                           | \
  69         CSPR_V)
  70 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  71 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  72                                 FTIM0_NOR_TEADC(0x5) | \
  73                                 FTIM0_NOR_TEAHC(0x5))
  74 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  75                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  76                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  77 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  78                                 FTIM2_NOR_TCH(0x4) | \
  79                                 FTIM2_NOR_TWPH(0x0E) | \
  80                                 FTIM2_NOR_TWP(0x1c))
  81 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  82 #define CONFIG_SYS_IFC_CCR      0x01000000
  83
  84 #ifndef CONFIG_SYS_NO_FLASH
  85 #define CONFIG_FLASH_CFI_DRIVER
  86 #define CONFIG_SYS_FLASH_CFI
  87 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  88 #define CONFIG_SYS_FLASH_QUIET_TEST
  89 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  90
  91 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
  92 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  93 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  94 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  95
  96 #define CONFIG_SYS_FLASH_EMPTY_INFO
  97 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  98                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  99 #endif
 100
 101 #define CONFIG_NAND_FSL_IFC
 102 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 103 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 104
 105
 106 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 107 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 108                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 109                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 110                                 | CSPR_V)
 111 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 112
 113 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 114                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 115                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 116                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 117                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 118                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 119                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 120
 121 #define CONFIG_SYS_NAND_ONFI_DETECTION
 122
 123 /* ONFI NAND Flash mode0 Timing Params */
 124 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 125                                         FTIM0_NAND_TWP(0x18)   | \
 126                                         FTIM0_NAND_TWCHT(0x07) | \
 127                                         FTIM0_NAND_TWH(0x0a))
 128 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 129                                         FTIM1_NAND_TWBE(0x39)  | \
 130                                         FTIM1_NAND_TRR(0x0e)   | \
 131                                         FTIM1_NAND_TRP(0x18))
 132 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 133                                         FTIM2_NAND_TREH(0x0a) | \
 134                                         FTIM2_NAND_TWHRE(0x1e))
 135 #define CONFIG_SYS_NAND_FTIM3           0x0
 136
 137 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 138 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 139 #define CONFIG_MTD_NAND_VERIFY_WRITE
 140 #define CONFIG_CMD_NAND
 141
 142 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 143
 144 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 145 #define QIXIS_LBMAP_SWITCH              0x06
 146 #define QIXIS_LBMAP_MASK                0x0f
 147 #define QIXIS_LBMAP_SHIFT               0
 148 #define QIXIS_LBMAP_DFLTBANK            0x00
 149 #define QIXIS_LBMAP_ALTBANK             0x04
 150 #define QIXIS_LBMAP_NAND                0x09
 151 #define QIXIS_RST_CTL_RESET             0x31
 152 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 153 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 154 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 155 #define QIXIS_RCW_SRC_NAND              0x107
 156 #define QIXIS_RST_FORCE_MEM             0x01
 157
 158 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 159 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 160                                 | CSPR_PORT_SIZE_8 \
 161                                 | CSPR_MSEL_GPCM \
 162                                 | CSPR_V)
 163 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 164                                 | CSPR_PORT_SIZE_8 \
 165                                 | CSPR_MSEL_GPCM \
 166                                 | CSPR_V)
 167
 168 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 169 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 170 /* QIXIS Timing parameters for IFC CS3 */
 171 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 172                                         FTIM0_GPCM_TEADC(0x0e) | \
 173                                         FTIM0_GPCM_TEAHC(0x0e))
 174 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 175                                         FTIM1_GPCM_TRAD(0x3f))
 176 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 177                                         FTIM2_GPCM_TCH(0xf) | \
 178                                         FTIM2_GPCM_TWP(0x3E))
 179 #define CONFIG_SYS_CS3_FTIM3            0x0
 180
 181 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
 182 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 183 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 184 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 185 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 186 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 187 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 188 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 189 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 190 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 191 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 192 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 193 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 194 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 195 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 196 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 197 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 198 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 199 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 200 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 201 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 202 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 203 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 204 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 205 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 206 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 207 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 208 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 209
 210 #define CONFIG_ENV_IS_IN_NAND
 211 #define CONFIG_ENV_OFFSET               (896 * 1024)
 212 #define CONFIG_ENV_SECT_SIZE            0x20000
 213 #define CONFIG_ENV_SIZE                 0x2000
 214 #define CONFIG_SPL_PAD_TO               0x20000
 215 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 * 1024)
 216 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 217 #else
 218 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 219 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 220 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 221 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 222 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 223 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 224 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 225 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 226 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 227 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 228 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 229 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 230 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 231 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 232 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 233 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 234 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 235 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 236 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 237 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 238 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 239 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 240 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 241 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 242 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 243 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 244 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 245
 246 #define CONFIG_ENV_IS_IN_FLASH
 247 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 248 #define CONFIG_ENV_SECT_SIZE            0x20000
 249 #define CONFIG_ENV_SIZE                 0x2000
 250 #endif
 251
 252 /* Debug Server firmware */
 253 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 254 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 255
 256 /* MC firmware */
 257 #define CONFIG_SYS_LS_MC_FW_IN_NOR
 258 #define CONFIG_SYS_LS_MC_FW_ADDR        0x580300000ULL
 259
 260 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
 261 #define CONFIG_SYS_LS_MC_DPL_ADDR       0x580700000ULL
 262
 263 #define CONFIG_SYS_LS_MC_DPC_IN_NOR
 264 #define CONFIG_SYS_LS_MC_DPC_ADDR       0x580800000ULL
 265
 266 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 267
 268 /*
 269  * I2C
 270  */
 271 #define I2C_MUX_PCA_ADDR                0x77
 272 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 273
 274 /* I2C bus multiplexer */
 275 #define I2C_MUX_CH_DEFAULT      0x8
 276
 277 /*
 278  * MMC
 279  */
 280 #ifdef CONFIG_MMC
 281 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 282         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 283 #endif
 284
 285 /*
 286  * RTC configuration
 287  */
 288 #define RTC
 289 #define CONFIG_RTC_DS3231               1
 290 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 291
 292 /* EEPROM */
 293 #define CONFIG_ID_EEPROM
 294 #define CONFIG_CMD_EEPROM
 295 #define CONFIG_SYS_I2C_EEPROM_NXID
 296 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 297 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 298 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 299 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 300 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 301
 302 #define CONFIG_FSL_MEMAC
 303 #define CONFIG_PCI              /* Enable PCIE */
 304 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 305
 306 #ifdef CONFIG_PCI
 307 #define CONFIG_PCI_PNP
 308 #define CONFIG_E1000
 309 #define CONFIG_PCI_SCAN_SHOW
 310 #define CONFIG_CMD_PCI
 311 #endif
 312
 313 /*  MMC  */
 314 #define CONFIG_MMC
 315 #ifdef CONFIG_MMC
 316 #define CONFIG_CMD_MMC
 317 #define CONFIG_FSL_ESDHC
 318 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 319 #define CONFIG_GENERIC_MMC
 320 #define CONFIG_CMD_FAT
 321 #define CONFIG_DOS_PARTITION
 322 #endif
 323
 324 /* Initial environment variables */
 325 #undef CONFIG_EXTRA_ENV_SETTINGS
 326 #define CONFIG_EXTRA_ENV_SETTINGS               \
 327         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 328         "loadaddr=0x80100000\0"                 \
 329         "kernel_addr=0x100000\0"                \
 330         "ramdisk_addr=0x800000\0"               \
 331         "ramdisk_size=0x2000000\0"              \
 332         "fdt_high=0xa0000000\0"                 \
 333         "initrd_high=0xffffffffffffffff\0"      \
 334         "kernel_start=0x581100000\0"            \
 335         "kernel_load=0xa0000000\0"              \
 336         "kernel_size=0x1000000\0"
 337
 338 #ifdef CONFIG_FSL_MC_ENET
 339 #define CONFIG_FSL_MEMAC
 340 #define CONFIG_PHYLIB
 341 #define CONFIG_PHYLIB_10G
 342 #define CONFIG_CMD_MII
 343 #define CONFIG_PHY_VITESSE
 344 #define CONFIG_PHY_REALTEK
 345 #define CONFIG_PHY_TERANETICS
 346 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 347 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 348 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 349 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 350
 351 #define CONFIG_MII              /* MII PHY management */
 352 #define CONFIG_ETHPRIME         "DPNI1"
 353 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 354
 355 #endif
 356
 357 #endif /* __LS2_QDS_H */