include/configs/lwmon.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /* External logbuffer support */
  32 #define CONFIG_LOGBUFFER
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC823           1       /* This is a MPC823E CPU        */
  40 #define CONFIG_LWMON            1       /* ...on a LWMON board          */
  41
  42 #define CONFIG_BOARD_PRE_INIT   1       /* Call board_pre_init          */
  43
  44 #define CONFIG_LCD              1       /* use LCD controller ...       */
  45 #define CONFIG_HLD1045          1       /* ... with a HLD1045 display   */
  46
  47 #if 1
  48 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  49 #else
  50 #define CONFIG_8xx_CONS_SCC2
  51 #endif
  52
  53 #define CONFIG_BAUDRATE         115200  /* with watchdog >= 38400 needed */
  54
  55 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second      */
  56
  57 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  58
  59 /* pre-boot commands */
  60 #define CONFIG_PREBOOT          "setenv bootdelay 15"
  61
  62 #undef  CONFIG_BOOTARGS
  63
  64 /* POST support */
  65 #define CONFIG_POST             (CFG_POST_CACHE    | \
  66                                  CFG_POST_WATCHDOG | \
  67                                  CFG_POST_RTC      | \
  68                                  CFG_POST_MEMORY   | \
  69                                  CFG_POST_CPU      | \
  70                                  CFG_POST_UART     | \
  71                                  CFG_POST_ETHER    | \
  72                                  CFG_POST_I2C      | \
  73                                  CFG_POST_SPI      | \
  74                                  CFG_POST_USB      | \
  75                                  CFG_POST_SPR)
  76
  77 #define CONFIG_BOOTCOMMAND      "run flash_self"
  78
  79 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
  80         "kernel_addr=40040000\0"                                                \
  81         "ramdisk_addr=40100000\0"                                               \
  82         "magic_keys=#3\0"                                                       \
  83         "key_magic#=28\0"                                                       \
  84         "key_cmd#=setenv addfb setenv bootargs \\$(bootargs) console=tty0\0"    \
  85         "key_magic3=24\0"                                                       \
  86         "key_cmd3=echo *** Entering Test Mode ***;" \
  87                 "setenv add_misc setenv bootargs \\$(bootargs) testmode\0"      \
  88         "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
  89         "ramargs=setenv bootargs root=/dev/ram rw\0"                            \
  90         "addfb=setenv bootargs $(bootargs) console=ttyS1,$(baudrate)\0"         \
  91         "addip=setenv bootargs $(bootargs) "                                    \
  92                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
  93                 "panic=1\0"                                                     \
  94         "add_wdt=setenv bootargs $(bootargs) $(wdt_args)\0"                     \
  95         "flash_nfs=run nfsargs addip add_wdt addfb;"            \
  96                 "bootm $(kernel_addr)\0"                                        \
  97         "flash_self=run ramargs addip add_wdt addfb;"           \
  98                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                        \
  99         "net_nfs=tftp 100000 /tftpboot/pImage.lwmon;"           \
 100                 "run nfsargs addip add_wdt addfb;bootm\0"       \
 101         "rootpath=/opt/eldk/ppc_8xx\0"                                          \
 102         "load=tftp 100000 /tftpboot/u-boot.bin\0"                               \
 103         "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $(filesize)\0"     \
 104         "wdt_args=wdt_8xx=off\0"                                                \
 105         "verify=no"
 106
 107 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 108 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 109
 110 #define CONFIG_WATCHDOG         1       /* watchdog enabled             */
 111
 112 #undef  CONFIG_STATUS_LED               /* Status LED disabled          */
 113
 114 /* enable I2C and select the hardware/software driver */
 115 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 116 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 117
 118 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 119 #define CFG_I2C_SLAVE           0xFE
 120
 121 #ifdef CONFIG_SOFT_I2C
 122 /*
 123  * Software (bit-bang) I2C driver configuration
 124  */
 125 #define PB_SCL          0x00000020      /* PB 26 */
 126 #define PB_SDA          0x00000010      /* PB 27 */
 127
 128 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 129 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 130 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 131 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 132 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 133                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 134 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 135                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 136 #define I2C_DELAY       udelay(1)       /* 1/4 I2C clock duration */
 137 #endif  /* CONFIG_SOFT_I2C */
 138
 139
 140 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 141
 142 #ifdef CONFIG_POST
 143 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
 144 #else
 145 #define CFG_CMD_POST_DIAG 0
 146 #endif
 147
 148 #ifdef CONFIG_8xx_CONS_SCC2     /* Can't use ethernet, then */
 149 #define CONFIG_COMMANDS      ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
 150                                 CFG_CMD_DATE    | \
 151                                 CFG_CMD_I2C     | \
 152                                 CFG_CMD_EEPROM  | \
 153                                 CFG_CMD_IDE     | \
 154                                 CFG_CMD_BSP     | \
 155                                 CFG_CMD_POST_DIAG )
 156 #else
 157 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 158                                 CFG_CMD_DHCP    | \
 159                                 CFG_CMD_DATE    | \
 160                                 CFG_CMD_I2C     | \
 161                                 CFG_CMD_EEPROM  | \
 162                                 CFG_CMD_IDE     | \
 163                                 CFG_CMD_BSP     | \
 164                                 CFG_CMD_POST_DIAG )
 165 #endif
 166 #define CONFIG_MAC_PARTITION
 167 #define CONFIG_DOS_PARTITION
 168
 169 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 170
 171 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 172 #include <cmd_confdefs.h>
 173
 174 /*----------------------------------------------------------------------*/
 175
 176 /*
 177  * Miscellaneous configurable options
 178  */
 179 #define CFG_LONGHELP                    /* undef to save memory         */
 180 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 181
 182 #undef  CFG_HUSH_PARSER                 /* enable "hush" shell          */
 183 #ifdef  CFG_HUSH_PARSER
 184 #define CFG_PROMPT_HUSH_PS2     "> "
 185 #endif
 186
 187 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 188 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 189 #else
 190 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 191 #endif
 192 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 193 #define CFG_MAXARGS     16              /* max number of command args   */
 194 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 195
 196 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 197 #define CFG_MEMTEST_END         0x00F00000      /* 1 ... 15MB in DRAM   */
 198
 199 #define CFG_LOAD_ADDR           0x00100000      /* default load address */
 200
 201 #define CFG_PIO_MODE            0       /* IDE interface in PIO Mode 0  */
 202
 203 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 204
 205 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 206
 207 /*
 208  * Low Level Configuration Settings
 209  * (address mappings, register initial values, etc.)
 210  * You should know what you are doing if you make changes here.
 211  */
 212 /*-----------------------------------------------------------------------
 213  * Internal Memory Mapped Register
 214  */
 215 #define CFG_IMMR                0xFFF00000
 216
 217 /*-----------------------------------------------------------------------
 218  * Definitions for initial stack pointer and data area (in DPRAM)
 219  */
 220 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 221 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 222 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 223 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 224 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 225
 226 /*-----------------------------------------------------------------------
 227  * Start addresses for the final memory configuration
 228  * (Set up by the startup code)
 229  * Please note that CFG_SDRAM_BASE _must_ start at 0
 230  */
 231 #define CFG_SDRAM_BASE          0x00000000
 232 #define CFG_FLASH_BASE          0x40000000
 233 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
 234 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 235 #else
 236 #define CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
 237 #endif
 238 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 239 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 240
 241 /*
 242  * For booting Linux, the board info and command line data
 243  * have to be in the first 8 MB of memory, since this is
 244  * the maximum mapped by the Linux kernel during initialization.
 245  */
 246 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 247 /*-----------------------------------------------------------------------
 248  * FLASH organization
 249  */
 250 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 251 #define CFG_MAX_FLASH_SECT      128     /* max number of sectors on one chip    */
 252
 253 #define CFG_FLASH_ERASE_TOUT    180000  /* Timeout for Flash Erase (in ms)      */
 254 #define CFG_FLASH_WRITE_TOUT    600     /* Timeout for Flash Write (in ms)      */
 255
 256 #if 1
 257 /* Put environment in flash which is much faster to boot */
 258 #define CFG_ENV_IS_IN_FLASH     1
 259 #define CFG_ENV_ADDR        0x40040000  /* Address    of Environment Sector     */
 260 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment            */
 261 #define CFG_ENV_SECT_SIZE       0x40000 /* we have BIG sectors only :-(         */
 262 #else
 263 /* Environment in EEPROM */
 264 #define CFG_ENV_IS_IN_EEPROM    1
 265 #define CFG_ENV_OFFSET          0
 266 #define CFG_ENV_SIZE            2048
 267 #endif
 268 /*-----------------------------------------------------------------------
 269  * I2C/EEPROM Configuration
 270  */
 271
 272 #define CFG_I2C_AUDIO_ADDR      0x28    /* Audio volume control                 */
 273 #define CFG_I2C_SYSMON_ADDR     0x2E    /* LM87 System Monitor                  */
 274 #define CFG_I2C_RTC_ADDR        0x51    /* PCF8563 RTC                          */
 275 #define CFG_I2C_POWER_A_ADDR    0x52    /* PCMCIA/USB power switch, channel A   */
 276 #define CFG_I2C_POWER_B_ADDR    0x53    /* PCMCIA/USB power switch, channel B   */
 277 #define CFG_I2C_KEYBD_ADDR      0x56    /* PIC LWE keyboard                     */
 278 #define CFG_I2C_PICIO_ADDR      0x57    /* PIC IO Expander                      */
 279
 280 #define CONFIG_USE_FRAM                 /* Use FRAM instead of EEPROM   */
 281 #ifdef CONFIG_USE_FRAM  /* use FRAM */
 282 #define CFG_I2C_EEPROM_ADDR     0x55    /* FRAM FM24CL64                */
 283 #define CFG_I2C_EEPROM_ADDR_LEN 2
 284 #else                   /* use EEPROM */
 285 #define CFG_I2C_EEPROM_ADDR     0x58    /* EEPROM AT24C164              */
 286 #define CFG_I2C_EEPROM_ADDR_LEN 1
 287 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* takes up to 10 msec  */
 288 #endif  /* CONFIG_USE_FRAM */
 289 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 290
 291 /* List of I2C addresses to be verified by POST */
 292 #define I2C_ADDR_LIST   {  /*   CFG_I2C_AUDIO_ADDR, */  \
 293                                 CFG_I2C_SYSMON_ADDR,    \
 294                                 CFG_I2C_RTC_ADDR,       \
 295                                 CFG_I2C_POWER_A_ADDR,   \
 296                                 CFG_I2C_POWER_B_ADDR,   \
 297                                 CFG_I2C_KEYBD_ADDR,     \
 298                                 CFG_I2C_PICIO_ADDR,     \
 299                                 CFG_I2C_EEPROM_ADDR,    \
 300                         }
 301
 302 /*-----------------------------------------------------------------------
 303  * Cache Configuration
 304  */
 305 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 306 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 307 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 308 #endif
 309
 310 /*-----------------------------------------------------------------------
 311  * SYPCR - System Protection Control                            11-9
 312  * SYPCR can only be written once after reset!
 313  *-----------------------------------------------------------------------
 314  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 315  */
 316 #if 0 && defined(CONFIG_WATCHDOG)       /* LWMON uses external MAX706TESA WD */
 317 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 318                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 319 #else
 320 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 321 #endif
 322
 323 /*-----------------------------------------------------------------------
 324  * SIUMCR - SIU Module Configuration                            11-6
 325  *-----------------------------------------------------------------------
 326  * PCMCIA config., multi-function pin tri-state
 327  */
 328 /* EARB, DBGC and DBPC are initialised by the HCW */
 329 /* => 0x000000C0 */
 330 #define CFG_SIUMCR      (SIUMCR_GB5E)
 331 /*#define CFG_SIUMCR    (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
 332
 333 /*-----------------------------------------------------------------------
 334  * TBSCR - Time Base Status and Control                         11-26
 335  *-----------------------------------------------------------------------
 336  * Clear Reference Interrupt Status, Timebase freezing enabled
 337  */
 338 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 339
 340 /*-----------------------------------------------------------------------
 341  * PISCR - Periodic Interrupt Status and Control                11-31
 342  *-----------------------------------------------------------------------
 343  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 344  */
 345 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 346
 347 /*-----------------------------------------------------------------------
 348  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 349  *-----------------------------------------------------------------------
 350  * Reset PLL lock status sticky bit, timer expired status bit and timer
 351  * interrupt status bit, set PLL multiplication factor !
 352  */
 353 /* 0x00405000 */
 354 #define CFG_PLPRCR_MF   4       /* (4+1) * 13.2 = 66 MHz Clock */
 355 #define CFG_PLPRCR                                                      \
 356                 (       (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |            \
 357                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 358                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 359                         PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/   \
 360                 )
 361
 362 #define CONFIG_8xx_GCLK_FREQ    ((CFG_PLPRCR_MF+1)*13200000)
 363
 364 /*-----------------------------------------------------------------------
 365  * SCCR - System Clock and reset Control Register               15-27
 366  *-----------------------------------------------------------------------
 367  * Set clock output, timebase and RTC source and divider,
 368  * power management and some other internal clocks
 369  */
 370 #define SCCR_MASK       SCCR_EBDF11
 371 /* 0x01800000 */
 372 #define CFG_SCCR        (SCCR_COM00     | /*SCCR_TBS|*/         \
 373                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 374                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 375                          SCCR_EBDF00 |   SCCR_DFSYNC00 |        \
 376                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 377                          SCCR_DFNH000   |   SCCR_DFLCD100 |     \
 378                          SCCR_DFALCD01)
 379
 380 /*-----------------------------------------------------------------------
 381  * RTCSC - Real-Time Clock Status and Control Register          11-27
 382  *-----------------------------------------------------------------------
 383  */
 384 /* 0x00C3 => 0x0003 */
 385 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 386
 387
 388 /*-----------------------------------------------------------------------
 389  * RCCR - RISC Controller Configuration Register                19-4
 390  *-----------------------------------------------------------------------
 391  */
 392 #define CFG_RCCR 0x0000
 393
 394 /*-----------------------------------------------------------------------
 395  * RMDS - RISC Microcode Development Support Control Register
 396  *-----------------------------------------------------------------------
 397  */
 398 #define CFG_RMDS 0
 399
 400 /*-----------------------------------------------------------------------
 401  *
 402  * Interrupt Levels
 403  *-----------------------------------------------------------------------
 404  */
 405 #define CFG_CPM_INTERRUPT       13      /* SIU_LEVEL6   */
 406
 407 /*-----------------------------------------------------------------------
 408  * PCMCIA stuff
 409  *-----------------------------------------------------------------------
 410  *
 411  */
 412 #define CFG_PCMCIA_MEM_ADDR     (0x50000000)
 413 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 414 #define CFG_PCMCIA_DMA_ADDR     (0x54000000)
 415 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 416 #define CFG_PCMCIA_ATTRB_ADDR   (0x58000000)
 417 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 418 #define CFG_PCMCIA_IO_ADDR      (0x5C000000)
 419 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 420
 421 /*-----------------------------------------------------------------------
 422  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 423  *-----------------------------------------------------------------------
 424  */
 425
 426 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 427
 428 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 429 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 430 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 431
 432 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 433 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 434
 435 #define CFG_ATA_IDE0_OFFSET     0x0000
 436
 437 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 438
 439 /* Offset for data I/O                  */
 440 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 441
 442 /* Offset for normal register accesses  */
 443 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 444
 445 /* Offset for alternate registers       */
 446 #define CFG_ATA_ALT_OFFSET      0x0100
 447
 448 /*-----------------------------------------------------------------------
 449  *
 450  *-----------------------------------------------------------------------
 451  *
 452  */
 453 /*#define       CFG_DER 0x2002000F*/
 454 #define CFG_DER 0
 455
 456 /*
 457  * Init Memory Controller:
 458  *
 459  * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
 460  */
 461
 462 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 463 #define FLASH_BASE1_PRELIM      0x41000000      /* FLASH bank #1        */
 464
 465 /* used to re-map FLASH:
 466  * restrict access enough to keep SRAM working (if any)
 467  * but not too much to meddle with FLASH accesses
 468  */
 469 #define CFG_REMAP_OR_AM         0xFF000000      /* OR addr mask */
 470 #define CFG_PRELIM_OR_AM        0xFF000000      /* OR addr mask */
 471
 472 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0        */
 473 #define CFG_OR_TIMING_FLASH     (OR_SCY_8_CLK)
 474
 475 #define CFG_OR0_REMAP   ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 476                                 CFG_OR_TIMING_FLASH)
 477 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
 478                                 CFG_OR_TIMING_FLASH)
 479 /* 16 bit, bank valid */
 480 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 481
 482 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 483 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 484 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 485
 486 /*
 487  * BR3/OR3: SDRAM
 488  *
 489  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 490  */
 491 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 492 #define SDRAM_PRELIM_OR_AM      0xF0000000      /* map 256 MB (>SDRAM_MAX_SIZE!) */
 493 #define SDRAM_TIMING            OR_SCY_0_CLK    /* SDRAM-Timing */
 494
 495 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB SDRAM */
 496
 497 #define CFG_OR3_PRELIM  (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
 498 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 499
 500 /*
 501  * BR5/OR5: Touch Panel
 502  *
 503  * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 504  */
 505 #define TOUCHPNL_BASE           0x20000000
 506 #define TOUCHPNL_OR_AM          0xFFFF8000
 507 #define TOUCHPNL_TIMING         OR_SCY_0_CLK
 508
 509 #define CFG_OR5_PRELIM  (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 510                          TOUCHPNL_TIMING )
 511 #define CFG_BR5_PRELIM  ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 512
 513 #define CFG_MEMORY_75
 514 #undef  CFG_MEMORY_7E
 515 #undef  CFG_MEMORY_8E
 516
 517 /*
 518  * Memory Periodic Timer Prescaler
 519  */
 520
 521 /* periodic timer for refresh */
 522 #define CFG_MPTPR       0x200
 523
 524 /*
 525  * MAMR settings for SDRAM
 526  */
 527
 528 #define CFG_MAMR_8COL   0x80802114
 529 #define CFG_MAMR_9COL   0x80904114
 530
 531 /*
 532  * MAR setting for SDRAM
 533  */
 534 #define CFG_MAR         0x00000088
 535
 536 /*
 537  * Internal Definitions
 538  *
 539  * Boot Flags
 540  */
 541 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 542 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 543
 544 #endif  /* __CONFIG_H */