include/configs/lwmon.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /* External logbuffer support */
  32 #define CONFIG_LOGBUFFER
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC823           1       /* This is a MPC823E CPU        */
  40 #define CONFIG_LWMON            1       /* ...on a LWMON board          */
  41
  42 #define CONFIG_BOARD_PRE_INIT   1       /* Call board_pre_init          */
  43 #define CONFIG_BOARD_POSTCLK_INIT 1     /* Call board_postclk_init      */
  44
  45 #define CONFIG_LCD              1       /* use LCD controller ...       */
  46 #define CONFIG_HLD1045          1       /* ... with a HLD1045 display   */
  47
  48 #define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  49
  50 #if 1
  51 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  52 #else
  53 #define CONFIG_8xx_CONS_SCC2
  54 #endif
  55
  56 #define CONFIG_BAUDRATE         115200  /* with watchdog >= 38400 needed */
  57
  58 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second      */
  59
  60 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  61
  62 /* pre-boot commands */
  63 #define CONFIG_PREBOOT          "setenv bootdelay 15"
  64
  65 #undef  CONFIG_BOOTARGS
  66
  67 /* POST support */
  68 #define CONFIG_POST             (CFG_POST_CACHE    | \
  69                                  CFG_POST_WATCHDOG | \
  70                                  CFG_POST_RTC      | \
  71                                  CFG_POST_MEMORY   | \
  72                                  CFG_POST_CPU      | \
  73                                  CFG_POST_UART     | \
  74                                  CFG_POST_ETHER    | \
  75                                  CFG_POST_I2C      | \
  76                                  CFG_POST_SPI      | \
  77                                  CFG_POST_USB      | \
  78                                  CFG_POST_SPR      | \
  79                                  CFG_POST_SYSMON)
  80
  81 #define CONFIG_BOOTCOMMAND      "run flash_self"
  82
  83 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  84         "kernel_addr=40080000\0"                                        \
  85         "ramdisk_addr=40280000\0"                                       \
  86         "magic_keys=#3\0"                                               \
  87         "key_magic#=28\0"                                               \
  88         "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
  89         "key_magic3=3C+3F\0"                                            \
  90         "key_cmd3=echo *** Entering Test Mode ***;"                     \
  91                 "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
  92         "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
  93         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  94         "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0"     \
  95         "addip=setenv bootargs $bootargs "                              \
  96                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
  97                 "panic=1\0"                                             \
  98         "add_wdt=setenv bootargs $bootargs $wdt_args\0"                 \
  99         "add_misc=setenv bootargs $bootargs runmode\0"                  \
 100         "flash_nfs=run nfsargs addip add_wdt addfb add_misc;"           \
 101                 "bootm $kernel_addr\0"                                  \
 102         "flash_self=run ramargs addip add_wdt addfb add_misc;"          \
 103                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 104         "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;"                   \
 105                 "run nfsargs addip add_wdt addfb;bootm\0"               \
 106         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
 107         "load=tftp 100000 /tftpboot/u-boot.bin\0"                       \
 108         "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
 109         "wdt_args=wdt_8xx=off\0"                                        \
 110         "verify=no"
 111
 112 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 113 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 114
 115 #define CONFIG_WATCHDOG         1       /* watchdog enabled             */
 116
 117 #undef  CONFIG_STATUS_LED               /* Status LED disabled          */
 118
 119 /* enable I2C and select the hardware/software driver */
 120 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 121 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 122
 123 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 124 #define CFG_I2C_SLAVE           0xFE
 125
 126 #ifdef CONFIG_SOFT_I2C
 127 /*
 128  * Software (bit-bang) I2C driver configuration
 129  */
 130 #define PB_SCL          0x00000020      /* PB 26 */
 131 #define PB_SDA          0x00000010      /* PB 27 */
 132
 133 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 134 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 135 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 136 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 137 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 138                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 139 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 140                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 141 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 142 #endif  /* CONFIG_SOFT_I2C */
 143
 144
 145 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 146
 147 #ifdef CONFIG_POST
 148 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
 149 #else
 150 #define CFG_CMD_POST_DIAG 0
 151 #endif
 152
 153 #ifdef CONFIG_8xx_CONS_SCC2     /* Can't use ethernet, then */
 154 #define CONFIG_COMMANDS      ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
 155                                 CFG_CMD_ASKENV  | \
 156                                 CFG_CMD_DATE    | \
 157                                 CFG_CMD_I2C     | \
 158                                 CFG_CMD_EEPROM  | \
 159                                 CFG_CMD_IDE     | \
 160                                 CFG_CMD_BSP     | \
 161                                 CFG_CMD_BMP     | \
 162                                 CFG_CMD_POST_DIAG )
 163 #else
 164 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 165                                 CFG_CMD_ASKENV  | \
 166                                 CFG_CMD_DHCP    | \
 167                                 CFG_CMD_DATE    | \
 168                                 CFG_CMD_I2C     | \
 169                                 CFG_CMD_EEPROM  | \
 170                                 CFG_CMD_IDE     | \
 171                                 CFG_CMD_BSP     | \
 172                                 CFG_CMD_BMP     | \
 173                                 CFG_CMD_POST_DIAG )
 174 #endif
 175 #define CONFIG_MAC_PARTITION
 176 #define CONFIG_DOS_PARTITION
 177
 178 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 179
 180 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 181 #include <cmd_confdefs.h>
 182
 183 /*----------------------------------------------------------------------*/
 184
 185 /*
 186  * Miscellaneous configurable options
 187  */
 188 #define CFG_LONGHELP                    /* undef to save memory         */
 189 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 190
 191 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
 192 #ifdef  CFG_HUSH_PARSER
 193 #define CFG_PROMPT_HUSH_PS2     "> "
 194 #endif
 195
 196 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 197 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 198 #else
 199 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 200 #endif
 201 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 202 #define CFG_MAXARGS     16              /* max number of command args   */
 203 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 204
 205 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 206 #define CFG_MEMTEST_END         0x00F00000      /* 1 ... 15MB in DRAM   */
 207
 208 #define CFG_LOAD_ADDR           0x00100000      /* default load address */
 209
 210 #define CFG_PIO_MODE            0       /* IDE interface in PIO Mode 0  */
 211
 212 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 213
 214 /*
 215  * When the watchdog is enabled, output must be fast enough in Linux.
 216  */
 217 #ifdef CONFIG_WATCHDOG
 218 #define CFG_BAUDRATE_TABLE      {               38400, 57600, 115200 }
 219 #else
 220 #define CFG_BAUDRATE_TABLE      {  9600, 19200, 38400, 57600, 115200 }
 221 #endif
 222
 223 /*
 224  * Low Level Configuration Settings
 225  * (address mappings, register initial values, etc.)
 226  * You should know what you are doing if you make changes here.
 227  */
 228 /*-----------------------------------------------------------------------
 229  * Internal Memory Mapped Register
 230  */
 231 #define CFG_IMMR                0xFFF00000
 232
 233 /*-----------------------------------------------------------------------
 234  * Definitions for initial stack pointer and data area (in DPRAM)
 235  */
 236 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 237 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 238 #define CFG_GBL_DATA_SIZE       68  /* size in bytes reserved for initial data */
 239 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 240 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 241
 242 /*-----------------------------------------------------------------------
 243  * Start addresses for the final memory configuration
 244  * (Set up by the startup code)
 245  * Please note that CFG_SDRAM_BASE _must_ start at 0
 246  */
 247 #define CFG_SDRAM_BASE          0x00000000
 248 #define CFG_FLASH_BASE          0x40000000
 249 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
 250 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 251 #else
 252 #define CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
 253 #endif
 254 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 255 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 256
 257 /*
 258  * For booting Linux, the board info and command line data
 259  * have to be in the first 8 MB of memory, since this is
 260  * the maximum mapped by the Linux kernel during initialization.
 261  */
 262 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 263 /*-----------------------------------------------------------------------
 264  * FLASH organization
 265  */
 266 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 267 #define CFG_MAX_FLASH_SECT      128     /* max number of sectors on one chip    */
 268
 269 #define CFG_FLASH_ERASE_TOUT    180000  /* Timeout for Flash Erase (in ms)      */
 270 #define CFG_FLASH_WRITE_TOUT    600     /* Timeout for Flash Write (in ms)      */
 271
 272 #if 1
 273 /* Put environment in flash which is much faster to boot */
 274 #define CFG_ENV_IS_IN_FLASH     1
 275 #define CFG_ENV_ADDR        0x40040000  /* Address    of Environment Sector     */
 276 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment            */
 277 #define CFG_ENV_SECT_SIZE       0x40000 /* we have BIG sectors only :-(         */
 278 #else
 279 /* Environment in EEPROM */
 280 #define CFG_ENV_IS_IN_EEPROM    1
 281 #define CFG_ENV_OFFSET          0
 282 #define CFG_ENV_SIZE            2048
 283 #endif
 284 /*-----------------------------------------------------------------------
 285  * I2C/EEPROM Configuration
 286  */
 287
 288 #define CFG_I2C_AUDIO_ADDR      0x28    /* Audio volume control                 */
 289 #define CFG_I2C_SYSMON_ADDR     0x2E    /* LM87 System Monitor                  */
 290 #define CFG_I2C_RTC_ADDR        0x51    /* PCF8563 RTC                          */
 291 #define CFG_I2C_POWER_A_ADDR    0x52    /* PCMCIA/USB power switch, channel A   */
 292 #define CFG_I2C_POWER_B_ADDR    0x53    /* PCMCIA/USB power switch, channel B   */
 293 #define CFG_I2C_KEYBD_ADDR      0x56    /* PIC LWE keyboard                     */
 294 #define CFG_I2C_PICIO_ADDR      0x57    /* PIC IO Expander                      */
 295
 296 #undef  CONFIG_USE_FRAM                 /* Use FRAM instead of EEPROM   */
 297
 298 #ifdef CONFIG_USE_FRAM  /* use FRAM */
 299 #define CFG_I2C_EEPROM_ADDR     0x55    /* FRAM FM24CL64                */
 300 #define CFG_I2C_EEPROM_ADDR_LEN 2
 301 #else                   /* use EEPROM */
 302 #define CFG_I2C_EEPROM_ADDR     0x58    /* EEPROM AT24C164              */
 303 #define CFG_I2C_EEPROM_ADDR_LEN 1
 304 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* takes up to 10 msec  */
 305 #endif  /* CONFIG_USE_FRAM */
 306 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 307
 308 /* List of I2C addresses to be verified by POST */
 309 #ifdef CONFIG_USE_FRAM
 310 #define I2C_ADDR_LIST   {  /*   CFG_I2C_AUDIO_ADDR, */  \
 311                                 CFG_I2C_SYSMON_ADDR,    \
 312                                 CFG_I2C_RTC_ADDR,       \
 313                                 CFG_I2C_POWER_A_ADDR,   \
 314                                 CFG_I2C_POWER_B_ADDR,   \
 315                                 CFG_I2C_KEYBD_ADDR,     \
 316                                 CFG_I2C_PICIO_ADDR,     \
 317                                 CFG_I2C_EEPROM_ADDR,    \
 318                         }
 319 #else   /* Use EEPROM - which show up on 8 consequtive addresses */
 320 #define I2C_ADDR_LIST   {  /*   CFG_I2C_AUDIO_ADDR, */  \
 321                                 CFG_I2C_SYSMON_ADDR,    \
 322                                 CFG_I2C_RTC_ADDR,       \
 323                                 CFG_I2C_POWER_A_ADDR,   \
 324                                 CFG_I2C_POWER_B_ADDR,   \
 325                                 CFG_I2C_KEYBD_ADDR,     \
 326                                 CFG_I2C_PICIO_ADDR,     \
 327                                 CFG_I2C_EEPROM_ADDR+0,  \
 328                                 CFG_I2C_EEPROM_ADDR+1,  \
 329                                 CFG_I2C_EEPROM_ADDR+2,  \
 330                                 CFG_I2C_EEPROM_ADDR+3,  \
 331                                 CFG_I2C_EEPROM_ADDR+4,  \
 332                                 CFG_I2C_EEPROM_ADDR+5,  \
 333                                 CFG_I2C_EEPROM_ADDR+6,  \
 334                                 CFG_I2C_EEPROM_ADDR+7,  \
 335                         }
 336 #endif  /* CONFIG_USE_FRAM */
 337
 338 /*-----------------------------------------------------------------------
 339  * Cache Configuration
 340  */
 341 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 342 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 343 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 344 #endif
 345
 346 /*-----------------------------------------------------------------------
 347  * SYPCR - System Protection Control                            11-9
 348  * SYPCR can only be written once after reset!
 349  *-----------------------------------------------------------------------
 350  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 351  */
 352 #if 0 && defined(CONFIG_WATCHDOG)       /* LWMON uses external MAX706TESA WD */
 353 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 354                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 355 #else
 356 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 357 #endif
 358
 359 /*-----------------------------------------------------------------------
 360  * SIUMCR - SIU Module Configuration                            11-6
 361  *-----------------------------------------------------------------------
 362  * PCMCIA config., multi-function pin tri-state
 363  */
 364 /* EARB, DBGC and DBPC are initialised by the HCW */
 365 /* => 0x000000C0 */
 366 #define CFG_SIUMCR      (SIUMCR_GB5E)
 367 /*#define CFG_SIUMCR    (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
 368
 369 /*-----------------------------------------------------------------------
 370  * TBSCR - Time Base Status and Control                         11-26
 371  *-----------------------------------------------------------------------
 372  * Clear Reference Interrupt Status, Timebase freezing enabled
 373  */
 374 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 375
 376 /*-----------------------------------------------------------------------
 377  * PISCR - Periodic Interrupt Status and Control                11-31
 378  *-----------------------------------------------------------------------
 379  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 380  */
 381 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 382
 383 /*-----------------------------------------------------------------------
 384  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 385  *-----------------------------------------------------------------------
 386  * Reset PLL lock status sticky bit, timer expired status bit and timer
 387  * interrupt status bit, set PLL multiplication factor !
 388  */
 389 /* 0x00405000 */
 390 #define CFG_PLPRCR_MF   4       /* (4+1) * 13.2 = 66 MHz Clock */
 391 #define CFG_PLPRCR                                                      \
 392                 (       (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |            \
 393                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 394                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 395                         PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/   \
 396                 )
 397
 398 #define CONFIG_8xx_GCLK_FREQ    ((CFG_PLPRCR_MF+1)*13200000)
 399
 400 /*-----------------------------------------------------------------------
 401  * SCCR - System Clock and reset Control Register               15-27
 402  *-----------------------------------------------------------------------
 403  * Set clock output, timebase and RTC source and divider,
 404  * power management and some other internal clocks
 405  */
 406 #define SCCR_MASK       SCCR_EBDF11
 407 /* 0x01800000 */
 408 #define CFG_SCCR        (SCCR_COM00     | /*SCCR_TBS|*/         \
 409                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 410                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 411                          SCCR_EBDF00 |   SCCR_DFSYNC00 |        \
 412                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 413                          SCCR_DFNH000   |   SCCR_DFLCD100 |     \
 414                          SCCR_DFALCD01)
 415
 416 /*-----------------------------------------------------------------------
 417  * RTCSC - Real-Time Clock Status and Control Register          11-27
 418  *-----------------------------------------------------------------------
 419  */
 420 /* 0x00C3 => 0x0003 */
 421 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 422
 423
 424 /*-----------------------------------------------------------------------
 425  * RCCR - RISC Controller Configuration Register                19-4
 426  *-----------------------------------------------------------------------
 427  */
 428 #define CFG_RCCR 0x0000
 429
 430 /*-----------------------------------------------------------------------
 431  * RMDS - RISC Microcode Development Support Control Register
 432  *-----------------------------------------------------------------------
 433  */
 434 #define CFG_RMDS 0
 435
 436 /*-----------------------------------------------------------------------
 437  *
 438  * Interrupt Levels
 439  *-----------------------------------------------------------------------
 440  */
 441 #define CFG_CPM_INTERRUPT       13      /* SIU_LEVEL6   */
 442
 443 /*-----------------------------------------------------------------------
 444  * PCMCIA stuff
 445  *-----------------------------------------------------------------------
 446  *
 447  */
 448 #define CFG_PCMCIA_MEM_ADDR     (0x50000000)
 449 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 450 #define CFG_PCMCIA_DMA_ADDR     (0x54000000)
 451 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 452 #define CFG_PCMCIA_ATTRB_ADDR   (0x58000000)
 453 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 454 #define CFG_PCMCIA_IO_ADDR      (0x5C000000)
 455 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 456
 457 /*-----------------------------------------------------------------------
 458  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 459  *-----------------------------------------------------------------------
 460  */
 461
 462 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 463
 464 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 465 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 466 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 467
 468 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 469 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 470
 471 #define CFG_ATA_IDE0_OFFSET     0x0000
 472
 473 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 474
 475 /* Offset for data I/O                  */
 476 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 477
 478 /* Offset for normal register accesses  */
 479 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 480
 481 /* Offset for alternate registers       */
 482 #define CFG_ATA_ALT_OFFSET      0x0100
 483
 484 /*-----------------------------------------------------------------------
 485  *
 486  *-----------------------------------------------------------------------
 487  *
 488  */
 489 #define CFG_DER 0
 490
 491 /*
 492  * Init Memory Controller:
 493  *
 494  * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
 495  */
 496
 497 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 498 #define FLASH_BASE1_PRELIM      0x41000000      /* FLASH bank #1        */
 499
 500 /* used to re-map FLASH:
 501  * restrict access enough to keep SRAM working (if any)
 502  * but not too much to meddle with FLASH accesses
 503  */
 504 #define CFG_REMAP_OR_AM         0xFF000000      /* OR addr mask */
 505 #define CFG_PRELIM_OR_AM        0xFF000000      /* OR addr mask */
 506
 507 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0        */
 508 #define CFG_OR_TIMING_FLASH     (OR_SCY_8_CLK)
 509
 510 #define CFG_OR0_REMAP   ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 511                                 CFG_OR_TIMING_FLASH)
 512 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
 513                                 CFG_OR_TIMING_FLASH)
 514 /* 16 bit, bank valid */
 515 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 516
 517 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 518 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 519 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 520
 521 /*
 522  * BR3/OR3: SDRAM
 523  *
 524  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 525  */
 526 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 527 #define SDRAM_PRELIM_OR_AM      0xF0000000      /* map 256 MB (>SDRAM_MAX_SIZE!) */
 528 #define SDRAM_TIMING            OR_SCY_0_CLK    /* SDRAM-Timing */
 529
 530 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB SDRAM */
 531
 532 #define CFG_OR3_PRELIM  (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
 533 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 534
 535 /*
 536  * BR5/OR5: Touch Panel
 537  *
 538  * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 539  */
 540 #define TOUCHPNL_BASE           0x20000000
 541 #define TOUCHPNL_OR_AM          0xFFFF8000
 542 #define TOUCHPNL_TIMING         OR_SCY_0_CLK
 543
 544 #define CFG_OR5_PRELIM  (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 545                          TOUCHPNL_TIMING )
 546 #define CFG_BR5_PRELIM  ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 547
 548 #define CFG_MEMORY_75
 549 #undef  CFG_MEMORY_7E
 550 #undef  CFG_MEMORY_8E
 551
 552 /*
 553  * Memory Periodic Timer Prescaler
 554  */
 555
 556 /* periodic timer for refresh */
 557 #define CFG_MPTPR       0x200
 558
 559 /*
 560  * MAMR settings for SDRAM
 561  */
 562
 563 #define CFG_MAMR_8COL   0x80802114
 564 #define CFG_MAMR_9COL   0x80904114
 565
 566 /*
 567  * MAR setting for SDRAM
 568  */
 569 #define CFG_MAR         0x00000088
 570
 571 /*
 572  * Internal Definitions
 573  *
 574  * Boot Flags
 575  */
 576 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 577 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 578
 579 #define CONFIG_MODEM_SUPPORT    1       /* enable modem initialization stuff */
 580 #undef CONFIG_MODEM_SUPPORT_DEBUG
 581
 582 #define CONFIG_MODEM_KEY_MAGIC  "3C+3F" /* press F3 + F6 keys to enable modem */
 583 #define CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 584 #endif  /* __CONFIG_H */